Virtual interconnections for reconfigurable logic systems
DCFirst Claim
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1. A reconfigurable electronic system comprising:
- a plurality of reprogrammable logic modules, each logic module having a plurality of pins for communicating signals external to the logic module and a plurality of logic elements for implementing logic in hardware;
inter-module connections between pins of different logic modules; and
a configurer for automatically configuring each logic module to define a partition of a specified target circuit with communications between the partitions of the target circuit being provided through pins and inter-module connections,a partition of the configured system having a number of inter-module communications to other partitions that exceeds the number of pins on the logic module of the partition and the logic module of the partition being configured to communicate through virtual interconnections in a time-multiplexed fashion through at least one pin of the logic module of the partition, the configurer determining a static virtual interconnection which includes a communication path extending through an intermediate reprogrammable logic module.
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Abstract
A compilation technique overcomes device pin limitations using virtual interconnections. Virtual interconnections overcome pin limitations by intelligently multiplexing each physical wire among multiple logical wires and pipelining these connections at the maximum clocking frequency. Virtual interconnections increase usable bandwidth and relax the absolute limits imposed on gate utilization in logic emulation systems employing Field Programmable Gate Arrays (FPGAs). A "softwire" compiler utilizes static routing and relies on minimal hardware support. The technique can be applied to any topology and FPGA device.
347 Citations
39 Claims
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1. A reconfigurable electronic system comprising:
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a plurality of reprogrammable logic modules, each logic module having a plurality of pins for communicating signals external to the logic module and a plurality of logic elements for implementing logic in hardware; inter-module connections between pins of different logic modules; and a configurer for automatically configuring each logic module to define a partition of a specified target circuit with communications between the partitions of the target circuit being provided through pins and inter-module connections, a partition of the configured system having a number of inter-module communications to other partitions that exceeds the number of pins on the logic module of the partition and the logic module of the partition being configured to communicate through virtual interconnections in a time-multiplexed fashion through at least one pin of the logic module of the partition, the configurer determining a static virtual interconnection which includes a communication path extending through an intermediate reprogrammable logic module. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A reconfigurable electronic system comprising:
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a plurality of reprogrammable logic modules, each logic module having an array of gates reconfigurable to define a hardware logic circuit and a plurality of pins for communicating signals external to the logic module; inter-module connections between pins of different logic modules; and a configurer for automatically configuring the array of gates, each logic module to define a partition of a specified target circuit with communications between the partitions of the target circuit being provided through pins and inter-module connections a partition of the configured system having a number of inter-module communications to other partitions that exceeds the number of pins on the logic module of the partition and gates of the logic module of the partition being configured as a multiplexer for receiving a plurality of outputs from the configured array of gates and for statically communicating the received outputs through a single pin in a multiplexed, pipelined fashion. - View Dependent Claims (18, 19)
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20. A reconfigurable electronic system comprising:
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a plurality of reprogrammable logic modules, each logic module having a plurality of pins for communicating signals external to the logic module and a plurality of logic elements for implementing logic in hardware; inter-module connections between pins of different logic modules; and a configurer for automatically configuring each logic module to define a partition of a specified target circuit with communications between the partitions of the target circuit being provided through pins and inter-module connections, a partition of the configured system having a number of inter-module communications to other partitions that exceeds the number of pins on the logic module of the partition and the logic module of the partition being configured to communicate through static virtual interconnections in a time-multiplexed fashion through at least one pin of the logic module of the partition, the electronic system including dedicated pins for providing a predetermined signal.
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21. A method of automatically compiling a reconfigurable digital system, comprising the steps of:
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partitioning a target circuit into a plurality of partitions, each partition to be configured into a reprogrammable logic module having a plurality of pins and a plurality of logic elements; configuring the logic modules to create partitions of the target circuit; determining static virtual interconnections between partitions corresponding to at least one common pin with signals along the virtual interconnections being time-multiplexed through the at least one common pin; and configuring the logic modules to route signals between logic modules through intermediate logic modules. - View Dependent Claims (22)
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23. A reconfigurable logic module comprising:
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an array of gates configurable to define a logic circuit; and a virtual interconnection comprising a plurality of gates reconfigured as a multiplexer, the multiplexer receiving a plurality of outputs from the configured gate array and communicating each of the received outputs through a single pin in a multiplexed, pipelined fashion. - View Dependent Claims (24, 25, 26, 27)
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28. A reconfigurable electronic system comprising
a plurality of reprogrammable logic modules, each logic module having a plurality of pins for communicating signals between logic modules; - and
a configurer to configure each logic module to define a partition of a specified target circuit, a partition of the configured target circuit having a number of interconnections to other partitions that exceeds the number of pins on the logic module and the logic module being configured to communicate through virtual interconnections through at least one pin. - View Dependent Claims (29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39)
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Specification