Register allocation method and apparatus for truncating runaway lifetimes of program variables in a computer system

• US 5,761,514 A
• Filed: 08/31/1995
• Issued: 06/02/1998
• Est. Priority Date: 08/31/1995
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Schmidt, William Jon, Roediger, Robert Ralph, Prosser, Edward Curtis, Aizikowitz, Nava Arela, Bar-Haim, Roy
• Primary Examiner(s): Voeltz, Emanuel Todd
• Assistant Examiner(s): CORCORAN, PETER JOSEPH
• Application Number:
  US08/522,052
• Time in Patent Office: 1,006 Days
• Field of Search: 395/705, 395/706, 395/707, 395/709, 395/708
• US Class Current: 717/158
• CPC Class Codes: G06F 8/433 Dependency analysis; Data or control flow analysis
• CPC Class Codes: G06F 8/441 Register allocation; Assignment of physical memory space to logical memory space

Abstract

A method and apparatus for truncating runaway lifetimes of program variables calculates liveness for each variable based on upwardly exposed uses. Reaching definitions are then calculated for at least the program variables that have runaway lifetimes. The liveness information is compared to the reaching definition information to determine whether a variable that is live upon entry to a basic block has a definition that reaches the end of each predecessor block, or has a use within the basic block. If the reaching definition for a variable reaches the beginning of the block and if there is a predecessor block for which there is no reaching definition, the variable has a runaway lifetime. The variable also has a runaway lifetime if there is a use of the variable in a block without a reaching definition for the variable at the beginning of the block. The runaway lifetime is truncated by inserting an instruction such as a pseudo-definition of the variable into the instruction stream at an appropriate place. Once runaway lifetimes are truncated using this method, subsequent stages of the compiler may calculate liveness by performing a single dataflow analysis which calculates lifetimes based on upwardly exposed uses.

Claims

1. A computer apparatus comprising:

(A) a central processing unit having a plurality of registers, the central processing unit executing a first instruction stream and in response to the first instruction stream, the central processing unit operates on information stored in the plurality of registers;

(B) a compiler for generating the first instruction stream from a second instruction stream, the second instruction stream having a plurality of variables, the compiler including;

a liveness calculator for determining for each of the plurality of variables a first span of the second instruction stream for which a selected one of the plurality of variables is live, wherein the selected variable is live at a first given point in the second instruction stream if the second instruction stream contains along some forward path from the first given point a first instruction that uses the selected variable before encountering a second instruction that defines the selected variable, and wherein the first span defines a lifetime for the selected variable;

a runaway lifetime detector for determining whether at least one of the plurality of variables is live in at least one predetermined location within the second instruction stream, wherein a variable that is live at the predetermined location has a runaway lifetime; and

a runaway lifetime truncator for inserting a third instruction into the second instruction stream to eliminate at least one runaway lifetime.

2. The computer apparatus of claim 1 further comprising a register allocator for assigning the plurality of registers within the central processing unit to the plurality of variables based on the lifetimes of the plurality of variables.

3. The computer apparatus of claim 1 wherein the first instruction stream comprises a first intermediate language instruction stream, wherein the second instruction stream comprises a second intermediate language instruction stream, and wherein the plurality of variables comprise a plurality of symbolic registers.

4. The computer apparatus of claim 1 wherein the third instruction comprises a pseudo-definition of one of the plurality of variables that has the runaway lifetime.

5. The computer apparatus of claim 1 wherein the predetermined location comprises the beginning of the second instruction stream.

6. The computer apparatus of claim 1 further comprising a reaching definitions calculator for determining for at least one of the plurality of variables a second span of the second instruction stream for which a selected one of the plurality of variables has a reaching definition, wherein the selected variable has a reaching definition at a second given point in the second instruction stream if the second instruction stream contains along some backward path from the second given point the second instruction that defines the selected variable.

7. The computer apparatus of claim 6 wherein the second instruction stream is divided into a plurality of basic blocks, and wherein the liveness calculator computes liveness for at least one of the plurality of variables at the beginning and at the end of each of the plurality of basic blocks, and wherein the reaching definitions calculator computes reaching definitions for at least one of the plurality of variables at the beginning and at the end of each of the plurality of basic blocks.

8. A computer apparatus for generating a first instruction stream executable on a central processing unit from a second instruction stream, the second instruction stream having a plurality of variables, the computer apparatus comprising:

a liveness calculator for determining for each of the plurality of variables a first span of the second instruction stream for which a selected one of the plurality of variables is live, wherein the selected variable is live at a first given point in the second instruction stream if the second instruction stream contains along some forward path from the first given point a first instruction that uses the selected variable before encountering a second instruction that defines the selected variable, and wherein the first span defines a lifetime for the selected variable;

a runaway lifetime detector for determining whether at least one of the plurality of variables is live in at least one predetermined location within the second instruction stream, wherein a variable that is live at the predetermined location has a runaway lifetime; and

a runaway lifetime truncator for inserting a third instruction into the second instruction stream to eliminate at least one runaway lifetime.

9. The computer apparatus of claim 8 further comprising a register allocator for assigning the plurality of registers within the central processing unit to the plurality of variables based on the lifetimes of the plurality of variables.

10. The computer apparatus of claim 8 wherein the first instruction stream comprises a first intermediate language instruction stream, wherein the second instruction stream comprises a second intermediate language instruction stream, and wherein the plurality of variables comprise a plurality of symbolic registers.

11. A program product comprising:

a recordable media; and

a compiler recorded on the recordable media, the compiler being used to generate a first instruction stream executable on a central processing unit in a computer apparatus from a second instruction stream, the second instruction stream having a plurality of variables, the compiler including;

a liveness calculator for determining for each of the plurality of variables a first span of the second instruction stream for which a selected one of the plurality of variables is live, wherein the selected variable is live at a first given point in the second instruction stream if the second instruction stream contains along some forward path from the first given point a first instruction that uses the selected variable before encountering a second instruction that defines the selected variable, and wherein the first span defines a lifetime for the selected variable;

a runaway lifetime detector for determining whether at least one of the plurality of variables is live in at least one predetermined location within the second instruction stream, wherein a variable that is live at the predetermined location has a runaway lifetime; and

a runaway lifetime truncator for inserting a third instruction into the second instruction stream to eliminate at least one runaway lifetime.

12. The computer apparatus of claim 11 further comprising a register allocator for assigning the plurality of registers within the central processing unit to the plurality of variables based on the lifetimes of the plurality of variables.

13. The computer apparatus of claim 11 wherein the first instruction stream comprises a first intermediate language instruction stream, wherein the second instruction stream comprises a second intermediate language instruction stream, and wherein the plurality of variables comprise a plurality of symbolic registers.

14. A method for determining the lifetimes of a plurality of variables within an instruction stream, comprising the steps of:

calculating at least one liveness bit vector corresponding to whether each of the plurality of variables is live at a particular location in the instruction stream, wherein the selected variable is live if the instruction stream contains along some forward path a first instruction that uses the selected variable before encountering a second instruction that defines the selected variable, and wherein a first span of the instruction stream for which the selected variable is live defines a lifetime for the selected variable;

determining from at least one of the liveness bit vectors whether at least one of the plurality of variables is live in at least one predetermined location within the second instruction stream, wherein a variable that is live at the predetermined location has a runaway lifetime; and

inserting at least one instruction into the instruction stream for truncating at least one of the runaway lifetimes.

15. The method of claim 14 further comprising the step of calculating at least one reaching definition bit vector for at least one of the plurality of variables that has a runaway lifetime, and inserting the at least one instruction based on the information contained within the at least one liveness bit vector and the at least one reaching definition bit vector.

16. The method of claim 14 wherein the step of inserting at least one instruction into the instruction stream comprises the step of inserting a pseudo-definition of at least one of the variables that has a runaway lifetime.

17. The method of claim 14 wherein the plurality of variables comprise a plurality of symbolic registers within the instruction stream.

18. The method of claim 14 further including the steps of:

dividing the second instruction stream into a plurality of basic blocks;

computing a liveness bit vector at the beginning and at the end of each of the plurality of basic blocks, each liveness bit vector including an indication of the liveness for at least one of the plurality of variables;

computing a reaching definitions bit vector at the beginning and at the end of each of the plurality of basic blocks, each reaching definitions bit vector including an indication of the reaching definition for at least one of the plurality of variables.

19. A computer implemented method for allocating a plurality of registers within a central processing unit to a plurality of variables within an instruction stream, comprising the steps of:

determining a plurality of lifetimes for the plurality of variables;

determining whether any of the lifetimes are runaway lifetimes by determining whether any of the plurality of variables are live at the beginning of the instruction stream;

truncating at least one runaway lifetime by inserting an instruction into the instruction stream;

building an interference graph with a plurality of nodes and a plurality of edges, each live range corresponding to one of the plurality of nodes in the interference graph, the edges of the interference graph representing interferences between nodes; and

coloring the interference graph with a number of colors not to exceed the number of the plurality of registers within the central processing unit.

20. A method for distributing a program product comprising the steps of:

initiating a connection between a first computer system and a second computer system;

transmitting the program product from the first computer system to the second computer system, the program product being a compiler, the compiler being used to generate a first instruction stream from a second instruction stream, the second instruction stream having a plurality of variables, the compiler including a liveness calculator for determining for each of the plurality of variables a first span of the second instruction stream for which a selected one of the plurality of variables is live, wherein the selected variable is live at a first given point in the second instruction stream if the second instruction stream contains along some forward path from the first given point a first instruction that uses the selected variable before encountering a second instruction that defines the selected variable, and wherein the first span defines a lifetime for the selected variable, and wherein the compiler further comprises a runaway lifetime detector for determining whether at least one of the plurality of variables is live in at least one predetermined location within the second instruction stream, wherein a variable that is live at the predetermined location has a runaway lifetime, and wherein the compiler further comprises a runaway lifetime truncator for inserting a third instruction into the second instruction stream to eliminate at least one runaway lifetime.