Single chip multiprocessor architecture with internal task switching synchronization bus
First Claim
1. A single-chip multiprocessor system, comprising:
- a first processor;
a second processor; and
a processor synchronization bus which interconnects said first and second processors;
said first processor being adapted, in response to a task more advantageously performed by said second processor, to enable said second processor to perform said task more advantageously performed by said second processor via said processor synchronization bus;
said second processor being adapted, in response to a task more advantageously performed by said first processor, to enable said first processor to perform said task more advantageously performed by said first processor via said processor synchronization bus.
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Accused Products
Abstract
A plurality of processors which can be the same or different are formed on a single integrated circuit chip together with a memory controller and an I/O controller, and are interconnected by a data transfer bus. The processors can have larger word lengths and operate at higher speeds than comparable single chip processors due to reduced latency and signal path lengths. The processors are further interconnected by a processor synchronization bus which enables one processor to cause another processor to perform a task by generating an interrupt and passing the required parameters. The parameters can be passed via shared memory, or via a bidirectional data section of the processor synchronization bus. A processor running a large scale CAD or similar application can cause a smaller processor to perform I/O tasks in native code. A multiprocessor system can be configured as including a Single-Chip module (SCM), a Multi-Chip Module (MCM), Board-Level Product (BPL), or as a box-level product which includes a power supply.
278 Citations
27 Claims
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1. A single-chip multiprocessor system, comprising:
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a first processor; a second processor; and a processor synchronization bus which interconnects said first and second processors; said first processor being adapted, in response to a task more advantageously performed by said second processor, to enable said second processor to perform said task more advantageously performed by said second processor via said processor synchronization bus; said second processor being adapted, in response to a task more advantageously performed by said first processor, to enable said first processor to perform said task more advantageously performed by said first processor via said processor synchronization bus. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A single-chip multiprocessor system, comprising:
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a first processor; a second processor; a processor synchronization bus which interconnects said first and second processors; a memory controller; an I/O controller; and a data bus to which said first and second processors, said memory controller and said I/O controller are connected; said first processor being adapted, in response to a task more advantageously performed by said second processor, to enable said second processor to perform said task more advantageously performed by said second processor via said processor synchronization bus; said second processor being adapted, in response to a task more advantageously performed by said first processor, to enable said first processor to perform said task more advantageously performed by said first processor via said processor synchronization bus. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
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25. A method of processing data using a multiprocessor system, in which:
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the multiprocessor system comprises; a first processor; a second processor; and a processor synchronization bus which interconnects said first and second processors and includes a first interrupt line and a second interrupt line said first processor being adapted, in response to a task more advantageously performed by said second processor, to enable said second processor to perform said task more advantageously performed by said second processor via said processor synchronization bus; said second processor being adapted, in response to a task more advantageously performed by said first processor, to enable said first processor to perform said task more advantageously performed by said first processor via said processor synchronization bus; and the method comprises controlling the first processor to cause the second processor to perform a task, including the steps of; (a) applying an interrupt to the second processor over the first interrupt line, and (b) passing parameters required for performing the task to the second processor. - View Dependent Claims (26, 27)
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Specification