Write cache for servicing write requests within a predetermined address range

• US 5,761,709 A
• Filed: 06/05/1995
• Issued: 06/02/1998
• Est. Priority Date: 06/05/1995
• Status: Expired due to Term

• Current Assignee: LG Electronics, Inc. (LG Corporation)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Kranich, Uwe
• Primary Examiner(s): Chan, Eddie P.
• Assistant Examiner(s): BRAGDON, REGINALD GLENWOOD
• Application Number:
  US08/464,352
• Time in Patent Office: 1,093 Days
• Field of Search: 395/470, 395/447, 395/448, 395/449, 395/471
• US Class Current: 711/122
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0848 Partitioned cache, e.g. separate instruction and operand caches
• CPC Class Codes: G06F 12/0879 Burst mode

Abstract

A memory system has a level 1 cache and a write cache connected to a processor, wherein the write cache has a memory address range and wherein the processor initiates a write to the write cache which is detected by the write cache. The write cache responds to the write request by storing information into the write cache if the write cache is not already full. If there is no storage location available in the write cache, a message is sent to the level 1 cache notifying that cache of this condition. The write cache responds to requests from the processor to write information stored in particular areas of the write cache into a main memory by placing that information on a external bus to be read by the main memory. The write cache then frees up those storage locations within the write cache to be used for storing subsequent writes requested by the processor.

Claims

1. A method for improving memory write performance in a processing system having a write cache which includes a plurality of storage locations and a first cache, the method comprising the steps of:

a) receiving a data write command which includes data and a memory address to write said data to; and

b) determining if said memory address is within a prespecified address range for the write cache, and if said memory address is within said prespecified address range;

i) determining if any of said storage locations are available for storing said memory address and said data corresponding to said memory address, and if there is at least one available storage location;

A) storing said data corresponding to said memory address in said at least one available storage location;

B) updating an availability status for each of said storage locations, and

C) writing said memory address and said data corresponding to said memory address on a respective external address bus and an external data bus upon receiving a burstwrite command which indicates that said memory address is to be written out,

wherein the step b) is only performed when said memory address corresponding to said data write request does not reside in said first cache.

2. A method as recited in claim 1, wherein said memory address and said data corresponding to said memory address are written out to a main memory connected to said external address bus and said external data bus.

3. A method as recited in claim 1, wherein in the step b), said memory address is compared with a maximum address value and a minimum address value, and when said memory address is both greater than said minimum address value and less than said maximum address value, said memory address is determined to be within said predetermined range, otherwise said memory address is determined to be outside said predetermined range.

4. A method as recited in claim 1, further comprising the step of:

D) sending a write cache hit signal to said first cache when said write cache writes said data corresponding to said memory address into said write cache.