Method and system for cache coherence despite unordered interconnect transport

• US 5,761,721 A
• Filed: 07/11/1996
• Issued: 06/02/1998
• Est. Priority Date: 12/28/1993
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Hoover, Russell Dean, Willis, John Christopher, Ziegler, Frederick Jacob, Baldus, Donald Francis, Duffield, Nancy Joan
• Primary Examiner(s): Swann, Tod R.
• Assistant Examiner(s): Thai, Tuan V.
• Application Number:
  US08/678,336
• Time in Patent Office: 691 Days
• Field of Search: 364/DIG. 1, 364/DIG. 2, 364/243.4, 364/243.41, 364/231.8, 364/238.4, 395/445, 395/420, 395/468, 395/481, 711/118, 711/210, 711/141, 711/154
• US Class Current: 711/141
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration
• CPC Class Codes: G06F 12/0815 Cache consistency protocols

Abstract

A method and system for providing cache coherence despite unordered interconnect transport. In a computer system of multiple memory devices or memory units having shared memory and an interconnect characterized by unordered transport, the method comprises sending a request packet over the interconnect from a first memory device to a second memory device requiring that an action be carried out on shared memory held by the second memory device. If the second memory device determines that the shared memory is in a transient state, the second memory device returns the request packet to the first memory device; otherwise, the request is carried out by the second memory device. The first memory device will continue to resend the request packet each time that the request packet is returned.

Claims

1. A method of operation for a state machine associated with a specific copy of a shared memory interval, said method comprising the steps of:

entering a first transient state from a stable functional state in response to initiation of a first transaction requesting a first action on a shared memory interval;

if initiation of a second transaction requesting a second action be performed on the shared memory interval is received while the state machine is in the first transient state, sending a conclusion to the second transaction directing that an initiator of the second transaction initiate a new transaction requesting the state machine to perform the second action;

entering a stable functional state from the first transient state when the first transaction is concluded by a response other than a request to generate a new transaction requesting the first action;

in response to receiving a conclusion to the first transaction that directs the initiator of the first transaction to initiate a new transaction requesting that the responder perform the first action, initiating a third transaction requesting the responder to perform the first action on the shared memory interval;

entering a second transient state from the first transient state in response to receiving, before the first transaction has concluded the initiation of a fourth transaction by the responder of the first transaction that requests a third action be performed on the shared memory interval;

if the initiation of a fifth transaction is received from an initiator other than the responder of the first transaction that requests a fourth action be performed on the shared memory interval while the state machine is in the second transient state, sending a conclusion to the fifth transaction directing that the initiator of the fifth transaction initiate a new transaction requesting the state machine to perform the fourth action; and

entering the stable functional state from the second transient state when the first transaction is concluded.

2. A method of operation for a state machine according to claim 1, wherein a shared memory is the requester of the first transaction.