Apparatus and method for implementing multiple scaled states in a state machine
First Claim
1. An integrated circuit comprising:
- a state machine having an state machine input line, a state machine clock line and a plurality of state machine output terminals, said state machine having a plurality of states, each state in said plurality being one of three types of states, a first scaled state, a second scaled state and an unscaled state;
wherein said state machine transitions from a current state of said plurality to a next state of said plurality in response to a clock signal on said state machine clock line if a first signal on said state machine input line is inactive,wherein said state machine stays in said current state in response to said clock signal if said first signal is active,wherein said state machine drives a second signal on said state machine output terminals on entry into said current state, said second signal being indicative of a duration of said state machine in said next state, andwherein a first duration in a first scaled state is larger than a second duration in a second scaled state, and said first duration is a multiple of a third duration in an unscaled state.
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Abstract
A state machine has states of three types: a fully scaled state, a partially scaled state and an unscaled state. The state machine (1) waits in the unscaled state for a minimum duration, (2) waits in the fully scaled state for a maximum duration that is a multiple of the minimum duration, and (3) waits in the partially scaled state for a duration smaller than the maximum duration but no smaller than the minimum duration. The state machine is included in a microprocessor chip, and is used to access an off-chip cache coupled to the microprocessor chip. The minimum and maximum durations are inverse of the respective clock frequencies of the microprocessor chip and of the off-chip cache. During a read access operation, the state machine waits in a partially scaled state while driving address signals of a to-be-retrieved word on an external bus coupled to the off-chip cache. Thereafter, the state machine waits in the fully scaled state on the external bus to access data signals driven by the off-chip cache to indicate the retrieved word. So, the state machine saves time by using the partially scaled state to set up address signals for a duration less than the maximum duration. Similarly, during a write access operation, the state machine also uses the partially scaled state to drive address signals and data signals of a to-be-written word to the off-chip cache.
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Citations
10 Claims
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1. An integrated circuit comprising:
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a state machine having an state machine input line, a state machine clock line and a plurality of state machine output terminals, said state machine having a plurality of states, each state in said plurality being one of three types of states, a first scaled state, a second scaled state and an unscaled state; wherein said state machine transitions from a current state of said plurality to a next state of said plurality in response to a clock signal on said state machine clock line if a first signal on said state machine input line is inactive, wherein said state machine stays in said current state in response to said clock signal if said first signal is active, wherein said state machine drives a second signal on said state machine output terminals on entry into said current state, said second signal being indicative of a duration of said state machine in said next state, and wherein a first duration in a first scaled state is larger than a second duration in a second scaled state, and said first duration is a multiple of a third duration in an unscaled state. - View Dependent Claims (2, 3, 4, 5, 6)
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7. In a computer system having a processor and memory addressable by said processor, said memory being capable of storing a plurality of words, said memory including at least a first level cache, a second level cache and a main memory, said first level cache being inside said processor, said second level cache and said main memory being outside said processor,
a second level control unit having a plurality of physical address terminals, said second level control unit including: -
a state machine having an state machine input line, a state machine clock line and a plurality of state machine output terminals, said state machine having a plurality of states, each state in said plurality being one of three types of states, a first scaled state, a second scaled state and an unscaled state; wherein said state machine transitions from a current state of said plurality to a next state of said plurality in response to a clock signal on said state machine clock line if a first signal on said state machine input line is inactive, wherein said state machine stays in said current state in response to said clock signal if said first signal is active, wherein said state machine drives a second signal on said state machine output terminals on entry into said current state, said second signal being indicative of a duration of said state machine in said next state, and wherein a first duration in a first scaled state is larger than a second duration in a second scaled state, and said first duration is a multiple of a third duration in an unscaled state; wherein said second level control unit uses said state machine to drive an address on said physical address signals to said second level cache. - View Dependent Claims (8)
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9. A method for operating a state machine in an integrated circuit, said state machine having an input line and a plurality of output terminals, said state machine having a plurality of states, each state in said plurality being one of three types of states, a first scaled state, a second scaled state and an unscaled state, said method comprising:
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transitioning said state machine from a current state to a next state in response to a clock signal if a first signal on said input line is inactive, keeping said state machine in said current state in response to said clock signal if said first signal is active, driving a second signal on said output terminals on entry into said current state, said second signal being indicative of a duration of said state machine in said next state, wherein a first duration of said state machine in a first scaled state is larger than a second duration in a second scaled state, and said first duration is a multiple of a third duration in an unscaled state. - View Dependent Claims (10)
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Specification