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Apparatus and method for implementing multiple scaled states in a state machine

  • US 5,761,736 A
  • Filed: 05/16/1996
  • Issued: 06/02/1998
  • Est. Priority Date: 05/16/1996
  • Status: Expired due to Term
First Claim
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1. An integrated circuit comprising:

  • a state machine having an state machine input line, a state machine clock line and a plurality of state machine output terminals, said state machine having a plurality of states, each state in said plurality being one of three types of states, a first scaled state, a second scaled state and an unscaled state;

    wherein said state machine transitions from a current state of said plurality to a next state of said plurality in response to a clock signal on said state machine clock line if a first signal on said state machine input line is inactive,wherein said state machine stays in said current state in response to said clock signal if said first signal is active,wherein said state machine drives a second signal on said state machine output terminals on entry into said current state, said second signal being indicative of a duration of said state machine in said next state, andwherein a first duration in a first scaled state is larger than a second duration in a second scaled state, and said first duration is a multiple of a third duration in an unscaled state.

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