Method for forming bumps on a substrate

• US 5,762,259 A
• Filed: 05/01/1997
• Issued: 06/09/1998
• Est. Priority Date: 07/13/1995
• Status: Expired due to Fees

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Hoebener, Karl G., Hubacher, Eric M.
• Primary Examiner(s): Ramsey, Kenneth J.
• Application Number:
  US08/848,792
• Time in Patent Office: 404 Days
• Field of Search: 228/248.1, 228/232, 228/180.22, 228/254, 437/183
• US Class Current: 228/180.22
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05671 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/11003 for holding or transferring the bump preform
• CPC Class Codes: H01L 2224/11334 using preformed bumps
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01022 Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H05K 2203/0113 : Female die used for patterning or transferring, e.g. temporary substrate having recessed pattern
• CPC Class Codes: H05K 2203/0338 : Transferring metal or conductive material other than a circuit pattern, e.g. bump, solder, printed component affixing a prefabricated conductor pattern H05K3/20
• CPC Class Codes: H05K 2203/043 : Reflowing of solder coated conductors, not during connection of components, e.g. reflowing solder paste
• CPC Class Codes: H05K 2203/0557 : Non-printed masks
• CPC Class Codes: H05K 3/1216 : by screen printing or stencil printing
• CPC Class Codes: H05K 3/3485 : Applying solder paste, slurry or powder thick film methods for applying conductive paste or ink patterns H05K3/12

Abstract

Solder bumps are formed on a substrate, such as a semiconductor die (28) or wafer, using a screen printing and reflow operation. Solder paste (18) is screened into openings (14) of a stencil (10). The paste is reflowed within the stencil to produce a solder preform (22). The stencil and solder preforms are then aligned over the substrate to be bumped so that the preform aligns with a metal pad (30) on the substrate. The solder preforms are again reflowed, and the solder within the openings of the stencil is drawn onto the metal pad. To facilitate the transfer of the solder from the stencil to the metal pad, a second stencil (12) can be used to form a protrusion (27) on the solder preform. The protrusion contacts the metal pad during the transfer reflow operation to facilitate removing the solder from the stencil.

Claims

1. A method for forming bumps on a substrate comprising the steps of:

providing a semiconductor substrate having a plurality of metal pads;

providing a first stencil having a plurality of openings corresponding in pattern to the plurality of metal pads;

providing a second stencil having a plurality of recesses, each recess having a corresponding opening of the plurality of openings in the first stencil;

bringing together the first stencil and the second stencil such that each recess aligns with its corresponding opening;

filling the plurality of recesses in the second stencil with the solder;

filling the plurality of openings in the first stencil with a solder;

reflowing the solder in the plurality of recesses and in the plurality of openings to form a plurality of solder preforms;

removing the second stencil from the first stencil;

positioning the first stencil over the semiconductor substrate such that the plurality of openings with the plurality of solder preforms formed therein is aligned to the plurality of metal pads; and

reflowing the solder preforms in the plurality of openings to form a solder bump on each of the plurality of metal pads.

2. The method of claim 1 wherein as a result of removing the second stencil, a protrusion is exposed for each solder preform.

3. The method of claim 2 wherein the step of positioning comprises positioning the first stencil over the semiconductor substrate such that the protrusion of each solder preform is in physical contact with a metal pad of the semiconductor substrate.

4. The method of claim 3 further comprising the step of placing a spacer in between the first stencil and the semiconductor substrate prior to the step of reflowing the solder preforms, wherein the spacer has a thickness less than a height of each protrusion.

5. A method for bumping a semiconductor wafer comprising the steps of:

providing a semiconductor wafer having a plurality of bump pads formed on a surface thereof;

providing a stencil made of a material that is non-wettable by a solder, the stencil having a plurality of openings, each opening having a uniform, controlled volume and including a recess;

dispensing the solder into the plurality of openings of the stencil;

firstly reflowing the solder in the stencil to form a plurality of solder preforms, each solder preform corresponding in size and shape to its respective opening including having a protrusion formed as a result of the recess;

positioning the stencil adjacent the semiconductor wafer such that the plurality of solder preforms aligns with and contacts the plurality of bumps pads via the protrusion of each solder perform; and

secondly reflowing the plurality of solder preforms while the stencil is still adjacent the semiconductor wafer to form a solder bump on each bump pad of the plurality of bumps pads.

6. The method of claim 5 wherein the step of providing a stencil comprises providing a stencil wherein each opening of the plurality of openings has a shape comprised of a truncated cone.

7. The method of claim 5 wherein the step of providing a stencil comprises providing a first stencil and a second stencil, wherein the first stencil defines the plurality of openings and the second stencil defines the recess of each opening, and wherein each opening of the plurality of openings extends completely through a thickness of the first stencil, wherein each opening has a first end at a first surface of the first stencil having a first width and has a second end at a second surface of the first stencil having a second width smaller than the first width, and wherein the step of positioning comprises positioning the first stencil over the semiconductor wafer such that second surface of the first stencil is closer to the semiconductor wafer than the first surface.

8. The method of claim 5 wherein the step of providing a stencil comprises providing a stencil wherein each opening of the plurality of openings has an opening width at a surface of the stencil which is adjacent the semiconductor wafer during the step of positioning, and wherein upon secondly reflowing, each solder bump has a bump width, and wherein the opening width of each opening is larger than the bump width of its corresponding solder bump.

9. The method of claim 5 wherein the step of providing a stencil comprises providing a first stencil, and further comprising the steps of:

providing a second stencil having the recess for each opening formed partially therethrough;

aligning the first stencil to the second stencil; and

dispensing the solder into the plurality of recesses in the second stencil;

wherein the step of firstly reflowing comprises firstly reflowing the solder in both the first and second stencils to form the plurality of solder preforms, including the protrusion for each solder preform.

10. The method of claim 9 further comprising the step of removing the second stencil to expose the protrusion on each solder preform, and wherein during the step of positioning, the protrusion of each solder preform is brought into physical contact with a bump pad of the semiconductor wafer.

11. The method of claim 10 further comprising the step of inserting a spacer between the semiconductor wafer and the first stencil, wherein the spacer is present during the step of secondly reflowing.

12. A method for forming bumps on a substrate comprising the steps of:

providing a substrate having a plurality of terminal pads;

providing a first stencil having a plurality of openings extending therethrough and corresponding in location to the plurality of terminal pads;

providing a second stencil having a plurality of recesses corresponding in location to the plurality of openings;

aligning the first stencil with the second stencil such that the plurality of recesses aligns with the plurality of openings;

dispensing solder into the plurality of openings and into the plurality of recesses;

reflowing the solder in the first stencil and the second stencil to form a plurality of solder preforms;

removing the second stencil, leaving the plurality of solder preforms within the first stencil;

aligning the first stencil with the substrate such that the plurality of solder preforms correspond in location with the plurality of terminal pads; and

reflowing the plurality of solder preforms to form a plurality of solder bumps on the plurality of terminal pads of the substrate.

13. The method of claim 12 wherein as a result of removing the second stencil, a plurality of protrusions of the plurality of solder preforms are exposed, wherein the plurality of protrusions are formed by the plurality of recesses of the second stencil.

14. The method of claim 13 wherein during the step of aligning, the plurality of protrusions are brought into physical contact with the plurality of terminal pads.

15. The method of claim 14 wherein the step of aligning the first stencil with the substrate comprises providing a spacer between the substrate and the first stencil.

16. The method of claim 12 wherein the step of providing a first stencil comprises providing a first stencil wherein each opening of the plurality of openings has a tapered sidewall.

17. The method of claim 16 wherein the step of aligning the first stencil with the substrate comprises aligning the first stencil over the substrate such that the tapered sidewall of each opening tapers inward to facilitate transfer of the solder from the first stencil to the plurality of terminal pads on the substrate during the step of reflowing the plurality solder preforms.

18. A method for forming bumps on a substrate comprising the steps of:

providing a semiconductor substrate having a plurality of metal pads;

providing a stencil having a plurality of openings corresponding in pattern to the plurality of metal pads;

filling the plurality of openings in the stencil with a solder;

providing a spacer between the stencil and the semiconductor substrate and positioning the stencil over the semiconductor substrate and spacer such that the plurality of openings with the solder therein is aligned to the plurality of metal pads;

reflowing the solder in the plurality of openings to form a solder bump on each of the plurality of metal pads; and

removing the spacer from the semiconductor substrate.

19. The method of claim 18 further comprising the step of reflowing the solder within the stencil to form a plurality of solder preforms, prior to positioning the stencil over the semiconductor substrate.

20. The method of claim 19 wherein as a result of reflowing the solder within the stencil to form a plurality of solder preforms, each solder preform has a protrusion, and wherein the step of positioning comprises positioning the stencil over the semiconductor substrate such that the protrusion from each solder preform is in contact with a metal pad of the plurality of metal pads.