Cell topology for power transistors with increased packing density

• US 5,763,914 A
• Filed: 07/16/1997
• Issued: 06/09/1998
• Est. Priority Date: 07/16/1997
• Status: Expired due to Term

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Megamos Corporation
• Inventors: Hshieh, Fwu-Iuan, Nim, Danny Chi
• Primary Examiner(s): MEIER, STEPHEN D
• Application Number:
  US08/895,507
• Time in Patent Office: 328 Days
• Field of Search: 257/329, 257/330, 257/341
• US Class Current: 257/329
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

The present invention discloses a power transistor cell supported on a semiconductor substrate with a top surface and a bottom surface. The power transistor cell includes a drain region, doped with impurities of a first conductivity type, formed at the bottom surface. The power transistor cell further includes a polysilicon gate layer overlaying the top surface includes a polysilicon opening disposed substantially in a central portion of the transistor cell with a remaining portion of the polysilicon layer constituting a gate and defining an outer boundary for the transistor cell wherein the polysilicon opening and the outer boundary defined by the gate for the transistor cell constituting substantially non-orthogonal parallelograms. The power transistor further includes a source region, doped with the first conductivity type, disposed in the substrate underneath and around an outer edge of the source opening with a small portion extends underneath the gate. The power transistor further includes a body region, doped with a second conductivity type, disposed in the substrate surrounding the source region and an entire portion of the substrate underneath the polysilicon opening having a small portion extends underneath the gate near the cell boundary. The packing density of the transistor cell is improved with the parallelogram cell occupies less areas than the regular square cell having the same total channel width.

Claims

1. A power transistor cell supported on a semiconductor substrate having a top surface and a bottom surface, the cell comprising:

a drain region, doped with impurities of a first conductivity type, formed at said bottom surface;

a polysilicon gate layer overlaying said top surface includes a polysilicon opening disposed substantially in a central portion of said transistor cell with a remaining portion of said polysilicon layer constituting a gate and defining an outer boundary for said transistor cell wherein said polysilicon opening and said outer boundary defined by said gate for said transistor cell constituting substantially non-orthogonal parallelograms;

a source region, doped with said first conductivity type, disposed in said substrate underneath and around an outer edge of said polysilicon opening with a small portion extends underneath said gate; and

a body region, doped with a second conductivity type, disposed in said substrate surrounding said source region and an entire portion of said substrate underneath said polysilicon opening having a small portion extends underneath said gate near said cell boundary.

2. The power transistor cell as recited in claim 1 wherein:

said first conductivity type is an N type conductivity and said transistor cell constituting an N-channel power transistor.

3. The power transistor cell as recited in claim 1 wherein:

said first conductivity type is an P type conductivity and said transistor cell constituting an P-channel power transistor.

4. The power transistor cell as recited in claim 1 wherein:

said polysilicon opening defining said non-orthogonal parallelogram with a sharp angle about sixty degrees (60°

).

5. The power transistor cell as recited in claim 1 wherein:

said polysilicon opening defining said non-orthogonal parallelogram with a sharp angle about forty-five degrees (45°

).

6. The power transistor cell as recited in claim 1 wherein:

said polysilicon opening defining said non-orthogonal parallelogram wherein two sharp angles are blunted.

7. The power transistor cell as recited in claim 1 wherein:

said polysilicon opening defining said non-orthogonal parallelogram wherein two sharp angles are rounded.

8. A power device includes a plurality of vertical MOSFET cells wherein each cell includes a drain disposed at a bottom surface of a substrate, a source region surrounded by a body region under a top surface of said substrate and a gate with a polysilicon opening disposed substantially near a center portion of said cell and overlaying a top surface of said substrate with a portion covering said source region and said body region thereunder wherein:

said polysilicon opening having a non-orthogonal parallelogram shape for each of said transistor cells.

9. The power device as recited in claim 8 wherein:

said transistor cells having said polysilicon opening of said non-orthogonal parallelogram shape are arranged with every four of said cells constituting substantially a non-orthogonal parallelogram shape.

10. The power device as recited in claim 8 wherein:

said transistor cells with said polysilicon opening of said non-orthogonal parallelogram shape are arranged with every four of said cells constituting sides of equal length.

11. The power device as recited in claim 8 wherein:

said transistor cells with said polysilicon opening of said non-orthogonal parallelogram shape are arranged with every seven of said cells constituting substantially a hexagonal shape including six outer cells defining a boundary of said hexagonal shape and one inner cell contained therein.

12. A vertical power transistor cell disposed on a semiconductor substrate provided as drain at a bottom surface and a source region, a gate disposed on a top surface, and a source and a body region each with a portion under the gate, wherein:

said gate defining a gate-layer opening constituting substantially a non-orthogonal parallelogram.

13. The vertical transistor cell as recited in claim 12 wherein:

said source region is doped with dopant of a first conductivity type and said first conductivity type is an N type conductivity and said transistor cell constituting an N-channel power transistor.

14. The vertical transistor cell as recited in claim 12 wherein:

said source region is doped with dopant of a first conductivity type and said first conductivity type is an P type conductivity and said transistor cell constituting an P-channel power transistor.

15. The vertical transistor cell as recited in claim 12 wherein:

said gate having an outer edge defining an outer boundary of said cell constituting substantially a non-orthogonal parallelogram.

16. The vertical transistor cell as recited in claim 12 wherein:

said gate layer opening defining said non-orthogonal parallelogram with a sharp angle about sixty degrees (60°

).

17. The power transistor cell as recited in claim 12 wherein:

said gate layer opening defining said non-orthogonal parallelogram with a sharp angle about forty-five degrees (45°

).

18. The power transistor cell as recited in claim 12 wherein:

said gate layer opening defining said non-orthogonal parallelogram wherein two sharp angles are blunted.

19. The power transistor cell as recited in claim 12 wherein:

said gate layer opening defining said non-orthogonal parallelogram wherein two sharp angles are rounded.

20. The vertical transistor cell as recited in claim 12 further comprising:

a source contact opening disposed near a center portion of said transistor cell provided for forming a source contact therein to contact said source region wherein said source contact opening constituting substantially a non-orthogonal parallelogram.

21. A trenched power transistor cell supported on a semiconductor substrate having a top surface and a bottom surface, the cell comprising:

a drain region, doped with impurities of a first conductivity type, formed at said bottom surface;

a trenched polysilicon gate disposed in a trench, opened from said top surface;

a source region, doped with said first conductivity type, disposed in said substrate immediately next to said and surrounding said trenched gate constituting substantially a ring of non-orthogonal parallelogram shape;

a body region, doped with a second conductivity type, disposed in said substrate surrounding and underneath said source region thus occupying an entire portion of said substrate underneath said source opening; and

an outer boundary of said cell defined by a central line of said trenched polysilicon gate constituting substantially a ring of non-orthogonal parallelogram shape.

22. The trenched power transistor cell as recited in claim 21 wherein:

said first conductivity type is an N type conductivity and said transistor cell constituting an N-channel trenched power transistor.

23. The trenched power transistor cell as recited in claim 21 wherein:

said first conductivity type is an P type conductivity and said transistor cell constituting an P-channel trenched power transistor.

24. The trenched power transistor cell as recited in claim 21 wherein:

said outer boundary of said transistor cell defined by said centerline of said trenched polysilicon gate constituting said non-orthogonal parallelogram having a sharp angle about sixty degrees (60°

).

25. The trenched power transistor cell as recited in claim 21 wherein:

said outer boundary of said transistor cell defined by said centerline of said trenched polysilicon gate constituting said non-orthogonal parallelogram having a sharp angle about forty-five degrees (45°

).

26. A trenched power device includes a plurality of vertical MOSFET cells wherein each cell includes a drain disposed at a bottom surface of a substrate, a trenched gate surrounding said cell, a source region disposed immediately next to said trenched gate surrounded by a body region under a top surface of said substrate with a source contact opening disposed substantially near a center portion of said cell and overlaying a top surface of said substrate with a portion covering said source region and said body region thereunder wherein:

a centerline of said trenched gate defining an outer boundary constituting a non-orthogonal parallelogram for each of said transistor cells.

27. The trenched power device as recited in claim 26 wherein:

said trenched transistor cells constituting said non-orthogonal parallelogram are arranged with every four of said cells constituting substantially a non-orthogonal parallelogram shape.

28. The trenched power device as recited in claim 26 wherein:

said trenched transistor cells constituting said non-orthogonal parallelogram are arranged with every four of said cells constituting sides of equal length.

29. The power device as recited in claim 26 wherein:

said trenched transistor cells constituting said non-orthogonal parallelogram are arranged with every seven of said cells constituting substantially a hexagonal shape including six outer cells defining a boundary of said hexagonal shape and one inner cell contained therein.

30. A trenched vertical power transistor cell disposed on a semiconductor substrate provided as drain at a bottom surface and a source region, a trenched gate disposed in a trench opened from a top surface, and a source and a body region each with a portion disposed next to the gate, wherein:

said trenched gate having centerline defining an outer boundary of said cell constituting substantially a non-orthogonal parallelogram.

31. The vertical transistor cell as recited in claim 30 wherein:

said source region is doped with dopant of a first conductivity type and said first conductivity type is an N type conductivity and said trenched transistor cell constituting an N-channel power transistor.

32. The vertical transistor cell as recited in claim 30 wherein:

said source region is doped with dopant of a first conductivity type and said first conductivity type is an P type conductivity and said trenched transistor cell constituting an P-channel power transistor.

33. The trenched transistor cell as recited in claim 30 further includes:

a source contact opening constituting substantially a non-orthogonal parallelogram near a center portion of said transistor cell.

34. The trenched transistor cell as recited in claim 30 wherein:

said outer boundary of said transistor cell defining said non-orthogonal parallelogram with a sharp angle about sixty degrees (60°

).

35. The power transistor cell as recited in claim 30 wherein:

said outer boundary of said transistor cell defining said non-orthogonal parallelogram with a sharp angle about forty-five degrees (45°

).

36. The power transistor cell as recited in claim 30 wherein:

said centerline of said trenched gate defining said non-orthogonal parallelogram with two sharp angles blunted.

37. The power transistor cell as recited in claim 30 wherein:

said centerline of said trenched gate defining said non-orthogonal parallelogram with two sharp angles rounded.