DMOS transistors having trenched gate oxide

• US 5,763,915 A
• Filed: 02/27/1996
• Issued: 06/09/1998
• Est. Priority Date: 02/27/1996
• Status: Expired due to Term

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Magemos Corporation
• Inventors: Hshieh, Fwu-Juan, So, Koon Chong, Tsui, Yan Man, Lin, True-Lon, Nim, Danny Chi
• Primary Examiner(s): Whitehead, Carl W.
• Application Number:
  US08/607,715
• Time in Patent Office: 833 Days
• Field of Search: 257/330, 257/334, 257/337, 257/338
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Improved power MOSFET structure, and fabrication process are disclosed in this invention to achieve cost savings by simplified device structure and fabrication processes, and also by reducing the required die size. Specifically, in a novel MOSFET device, insulation of mobile ions are achieved by extending the poly gate and metal contacts such that the passivation layer is no longer required and the fabrication process is simplified such that the MOSFET device can be manufactured at a lower price. Furthermore, in another MOSFET device, the gate runner is used to replace the field plate such that the requirement of a field plate as that in a conventional MOSFET device is also eliminated and, by reducing the die size, the cost of manufacture is further reduced.

Claims

1. A DMOS device includes a core cell area comprising a plurality of trenched DMOS cells and a gate metal area for forming a gate metal therein near a termination area disposed on an outer peripheral of said DMOS device, wherein said DMOS device include a plurality of trenched poly-fingers extending from trenched poly-gates of said DMOS cells to said gate metal area provided with a trench-end region defining a plurality of trench corners therein, said DMOS device further comprising:

an above-trench poly-runner layer covering said gate metal area including said trench-end region and said above-trench poly-runner layer is connected to said poly-fingers wherein said above-trench poly runner layer defining a plurality of gate contact openings provided for depositing a metal therein to contact said trenched poly-fingers and said trenched gates; and

a gate contact opening is disposed above each of said trench corners whereby none of said trench corners being covered by said above-trench poly-runner layer.

2. The DMOS transistor as recited in claim 1 wherein:

said poly fingers extending to and terminating at said trench-end region thus defining a plurality of trench ends therein, wherein a gate contact opening is disposed above each of said trench end.

3. The DMOS transistor as recited in claim 1 wherein:

said trench-end region includes a gate-runner connected to an end point of said poly-fingers thus defining a plurality of trench corners therein, wherein a gate contact window is disposed above each of said trench corners whereby none of said trench corners being covered by said above-trench poly-runner layer.

4. A trenched DMOS device with no above trench poly layer includes a core cell area comprising a plurality of trenched DMOS cells and a gate metal area for forming a gate metal therein near a termination area disposed on an outer peripheral of said DMOS device, wherein said trenched DMOS device includes a plurality of trenched poly-fingers extending from trenched poly-gates of said DMOS cells to said gate metal area thus forming a trench-end region, said DMOS device further comprising:

a trenched gate-runner having a width substantially larger than said poly-fingers in said trench-end region comprising trenched polysilicon and connected to an end point of said poly-fingers wherein said trenched polysilicon in said trenched gates, said poly-fingers and said gate runner are disposed in said trenches whereby said DMOS device includes no above trench polysilicon layer in contact with said trenched polysilicon; and

an insulation layer covering an entire area around said trench-end region wherein said insulation layer defining a plurality of openings provided for metal contacts including a plurality of gate contact openings above said gate runner provided for filling a gate metal therein for contacting said poly-fingers and said gate therefrom.

5. The DMOS device as recited in claim 4 wherein:

said trenched gates and poly-fingers extended therefrom having a width of approximately 1.0 micrometer and said gate runner having a width ranging from two to four microns (2.0-4.0 μ

s).

6. The DMOS device as recited in claim 4 further comprising:

a mobile ion blocking layer disposed under said insulation layer covering an enter top surface of said DMOS device other than said openings for provided for metal contacts.

7. The DMOS device as recited in claim 4 further comprising:

several floating ring regions of a conductivity type same as said body region disposed in said termination area next to said gate runner.