Circuits and methods for compensating non-linear capacitances to minimize harmonic distortion

• US 5,763,924 A
• Filed: 05/09/1996
• Issued: 06/09/1998
• Est. Priority Date: 05/09/1996
• Status: Expired due to Term

• Current Assignee: Analog Devices International Unlimited Company (Analog Devices, Inc.)
• Original Assignee: Linear Technology Corporation (Analog Devices, Inc.)
• Inventors: Lum, Sammy S., Rempfer, William C.
• Primary Examiner(s): Ngo , Ngan V.
• Application Number:
  US08/647,361
• Time in Patent Office: 761 Days
• Field of Search: 257/386, 257/401, 327/341, 327/362
• US Class Current: 257/386
• CPC Class Codes: G11C 27/02 Sample-and-hold arrangements G11C27/04 takes precedence
• CPC Class Codes: G11C 27/024 using a capacitive memory element G11C27/04 takes precedence
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors

Abstract

A simple, low-cost circuit and method for line zing parasitic capacitances of transistor junctions, independent of the process technology employed, are provided. In the preferred embodiment, the parasitic capacitance of a transistor in a track and hold circuit is linearized by providing a pair of diodes that act inversely to the parasitic diodes formed within the integrated circuit during normal tracking operations. Without the diodes of the present invention, the varying input signals cause the parasitic capacitance to vary, thereby causing harmonic distortion in the track and hold circuit. An alternate embodiment of the present invention is also provided in which a second complementary transistor is provided. The inclusion of the complementary transistor results in a second set of parasitic capacitances that are substantially opposite the parasitic capacitances of the track and hold transistor. Additionally, depending on the ratios of the various components, the techniques of the two embodiments may be, combined, such that additional diode may be added even if the complementary transistor technique is utilized.

Claims

1. A method of linearizing parasitic junction capacitances in a circuit employing a transistor having drain, gate and source terminals, said method comprising the steps of:

providing a bias voltage to the circuit at a bias voltage terminal;

inserting a first diode between the source terminal of the transistor and the bias voltage terminal; and

inserting a second diode between the drain terminal of the transistor and the bias voltage terminal.

2. A method of linearizing parasitic junction capacitances in an integrated circuit track and hold circuit, employing a transistor having drain, gate and source terminals, said method comprising the steps of:

receiving a voltage varying input at the source terminal of the transistor;

receiving a trigger input at the gate terminal of the transistor;

compensating for parasitic junction capacitances of the transistor by providing a bias voltage at a bias voltage terminal, adding a first diode between the source terminal of the transistor and the bias voltage terminal, and adding a second diode between the drain terminal of the transistor and the bias voltage terminal;

providing an output at the drain terminal of the transistor.

3. A parisitic-junction-capacitance-compensated circuit comprising:

a bias voltage terminal;

a transistor having source, drain and gate terminals;

a first diode, coupled between the drain terminal and the bias voltage terminal, that compensates for parasitic junction capacitance of the drain terminal; and

a second diode, coupled between the source terminal and the bias voltage terminal, that compensates for parasitic junction capacitance of the source terminal.

4. A parasitic-junction-capacitance-compensated track and hold circuit having an input and an output and a trigger, said track and hold circuit comprising:

a bias voltage terminal;

a transistor having source, drain and gate terminals;

a capacitor coupled between the drain terminal and ground;

a first diode, coupled between the drain terminal and the bias voltage terminal, that compensates parasitic junction capacitance of the drain terminal; and

a second diode, coupled between the source terminal and the bias voltage terminal, that compensates for parasitic junction capacitance of the source terminal;

wherein a voltage varying input signal is received at the input, and upon the trigger, alternatively outputting;

(1) a varying signal substantially equal to the input signal;

or (2) a constant signal substantially equal to the value of the input signal when the trigger was received.

5. The track and hold circuit of claim 4, wherein the bias voltage terminal, the transistor, the capacitor and the first and second diodes comprise a single integrated circuit.

6. The track and hold circuit of claim 4, wherein the transistor is an n-type transistor.

7. The track and hold circuit of claim 4, wherein the transistor is a p-type transistor.

8. A parasitic-junction-capacitance-compensated track and hold circuit comprising:

a bias voltage node;

a transistor having a source, a drain and a gate;

a capacitor coupled between the drain and ground;

a first diode, coupled between the drain and the bias voltage node, that compensates for parasitic junction capacitance of the drain; and

a second diode, coupled between the source and the bias voltage node, that compensates for parasitic junction capacitance of the source;

wherein a voltage varying input signal is received at the source and a trigger signal is received at the gate to alternatively provide as output at the drain;

(1) the voltage varying input signal, or (2) a constant signal of voltage substantially equal to the input signal upon receipt of the trigger signal.

9. The track and hold circuit of claim 8, wherein the bias voltage node, the transistor, the capacitor and the first and second diodes comprise a single integrated circuit.

10. The track and hold circuit of claim 8, wherein the transistor is an n-type transistor.

11. The track and hold circuit of claim 8, wherein the transistor is a p-type transistor.

12. A parasitic-junction-capacitance-compensated track and hold circuit comprising:

first and second transistors of complementary types, each transistor having a source, a drain and a gate, and there being parasitic junction capacitance associated with the source-gate and drain-gate junctions, the first and second transistors having commonly coupled sources and commonly coupled drains;

a capacitor coupled between ground and the drains of the first and second transistor;

wherein a voltage varying input signal is received at the sources of the first and second transistors and a trigger signal is received at the gates of the first and second transistors to alternatively provide as output at the drain;

(1) the voltage-varying input signal, or (2) a constant signal of voltage substantially equal to the input signal upon receipt of the trigger signal; and

wherein the parasitic capacitances of the source-gate and drain-gate junctions of the second transistor linearize the parasitic capacitances of the source-gate and drain-gate junctions of the first transistor.

13. The track and hold circuit of claim 12, wherein the first and second transistors and the capacitor comprise a single integrated circuit.

14. The track and hold circuit of claim 13, further comprising:

a bias voltage terminal;

a first diode, coupled between the drain of the first transistor and the bias voltage terminal, that compensates for parasitic junction capacitances of the drain of the first transistor; and

a second diode, coupled between the source of the first transistor and the bias voltage terminal, that compensates for parasitic junction capacitance of the source of the first transistor.

15. The track and hold circuit of claim 14, wherein the first and second diodes further comprise the single integrated circuit.

16. The track and hold circuit of claim 13, further comprising:

a bias voltage terminal;

a first diode, coupled between the drain of the first transistor and the bias voltage terminal, that compensates for parasitic junction capacitances of the drain of the second transistor; and

a second diode, coupled between the source of the first transistor and the bias voltage terminal, that compensates for parasitic junction capacitance of the source of the second transistor.

17. The track and hold circuit of claim 16, wherein the first and second diodes further comprise the single integrated circuit.