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Circuits and methods for compensating non-linear capacitances to minimize harmonic distortion

  • US 5,763,924 A
  • Filed: 05/09/1996
  • Issued: 06/09/1998
  • Est. Priority Date: 05/09/1996
  • Status: Expired due to Term
First Claim
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1. A method of linearizing parasitic junction capacitances in a circuit employing a transistor having drain, gate and source terminals, said method comprising the steps of:

  • providing a bias voltage to the circuit at a bias voltage terminal;

    inserting a first diode between the source terminal of the transistor and the bias voltage terminal; and

    inserting a second diode between the drain terminal of the transistor and the bias voltage terminal.

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