Structure for testing bare integrated circuit devices

• US 5,764,070 A
• Filed: 02/21/1996
• Issued: 06/09/1998
• Est. Priority Date: 02/28/1995
• Status: Expired due to Fees

• Current Assignee: Mitel Semiconductor, Limited (Microchip Technology Incorporated)
• Original Assignee: Plessey Semiconductors Limited (Plessey Group Holdings Ltd.)
• Inventors: Pedder, David John
• Primary Examiner(s): Karlsen, Ernest F.
• Assistant Examiner(s): PHUNG, ANH K
• Application Number:
  US08/603,602
• Time in Patent Office: 839 Days
• Field of Search: 324/754, 324/755, 324/762
• US Class Current: 324/754.03
• CPC Class Codes: G01R 1/06772 High frequency probes
• CPC Class Codes: G01R 31/2805 Bare printed circuit boards

Abstract

A test probe structure for making connections to a bare integrated circuit device or a wafer to be tested comprises a multilayer printed circuit probe arm which carries at its tip an MCM-D type substrate having a row of microbumps on its underside to make the required connections. The probe arm is supported at a shallow angle to the surface of the device or wafer, and the MCM-D type substrate is formed with the necessary passive components to interface with the device under test. Four such probe arms may be provided, one on each side of the device under test.

Claims

1. A structure for testing bare integrated circuit devices, comprising:

device support means for supporting an integrated circuit device to be tested;

a substrate having formed on one surface thereof a multilayer metal-polyimide dielectric interconnect structure; and

a multilayer printed circuit board probe means for supporting said substrate at an angle with respect to said device such that an edge of said one surface of said substrate is adjacent said device, said substrate being secured to an end of said printed circuit board probe means by a thermoplastic adhesive, said multilayer interconnect structure having a plurality of contact pads formed along said edge of said substrate and a like plurality of microbump contacts formed on respective ones of said plurality of contact pads.

2. A structure in accordance with claim 1 wherein the substrate comprises a sapphire wafer.

3. A structure in accordance with claim 1 wherein the substrate comprises a silicon wafer.

4. A structure in accordance with claim 1 wherein the multi-layer metal-polymer dielectric substrate incorporates a plurality of passive circuit components.

5. A structure in accordance with claim 1 wherein electrical connections between the substrate and conductors on the printed circuit board probe means are made by way of short wire bond links.

6. A structure in accordance with claim 5 wherein said conductors on the printed circuit board probe means provide power supply, ground and signal lines.

7. A structure in accordance with claim 1 including at least one discrete circuit component mounted on said printed circuit board probe means adjacent said substrate and electrically connected to said interconnect structure.

8. A structure in accordance with claim 1 wherein there are provided a plurality of said printed circuit board probe means each having a respective substrate secured thereto to make contact to said integrated circuit device to be tested.