Circuits, systems and methods for transferring data across a conductive line

• US 5,764,082 A
• Filed: 07/29/1996
• Issued: 06/09/1998
• Est. Priority Date: 07/29/1996
• Status: Expired due to Term

• Current Assignee: Intellectual Ventures II LLC (Intellectual Ventures LLC)
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Taylor, Ronald T.
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US08/681,661
• Time in Patent Office: 680 Days
• Field of Search: 326/81, 326/80, 326/86, 326/88, 326/90, 326/92
• US Class Current: 326/81
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H03K 19/01855 synchronous, i.e. using clock signals

Abstract

A system 500 is provided for transferring signals across a bus which includes a power source 550 operating between a high voltage rail at a first supply voltage level and a low voltage rail at a second supply voltage rail, power source 550 generating a third supply voltage level on an output thereto. The third supply voltage level is greater than the first supply voltage level. A processing circuitry 103, 104 is included for generating a plurality of data signals each having a first voltage swing between a first logic high level substantially equal to the first supply voltage level and a first logic low level substantially equal to the second supply voltage level. The system additionally includes a plurality of buffers, 520, each buffer 520 being coupled to the power source 550 output and receiving a selected one of the data signals. Each buffer 520 generates a boosted drive signal having a second voltage swing between a second logic high level substantially equal to the third supply voltage level and a second logic low level substantially equal to the second supply voltage level.

Claims

1. A system for transferring signals across a bus, said system comprising

a power source operating between a high voltage rail at a first voltage level and a low voltage rail at a second supply voltage level, said power source generating a third supply voltage level on an output of said power source, wherein said third supply voltage level is greater than said first supply voltage level;

processing circuitry generating a plurality of data signals having a first voltage swing between a first logic high level substantially equal to said first supply voltage level and a first logic low level substantially equal to said second supply voltage level; and

a plurality of level shifting circuits, wherein each of said level shifting circuits is coupled to said power source output and receives a selected one of said data signals, and wherein each of said level shifting circuits generates a boosted drive signal having a second voltage swing between a second logic high level substantially equal to said third supply voltage level and a second logic low level substantially equal to said second supply voltage level.

2. The system as set forth in claim 1 further comprising a plurality of output stages, each of said output stages receiving a selected one of said boosted drive signals and comprising:

a first N-channel transistor having a source coupled to a selected one of said plurality of conductive lines and a drain coupled to said high voltage rail; and

a second N-channel transistor having a drain coupled to said selected conductive line and a source coupled to said low voltage rail.

3. The system as set forth in claim 2 wherein said third supply voltage level greater than said first supply voltage level by at least a threshold voltage of said first N-channel transistor.

4. The system as set forth in claim 1 wherein said power source comprises:

a storage capacitor for storing a charge; and

a charge pump for charging said storage capacitor to said third voltage supply level.

5. The system as set forth in claim 4 wherein said charge pump comprises:

a second capacitor;

circuitry for charging said second capacitor; and

circuitry for selectively coupling charge from said second capacitor to said storage capacitor.

20. The integrated circuit as set forth in claim 1 wherein said power source comprises:

a storage capacitor for storing a charge; and

a charge pump for charging said storage capacitor to said voltage V_PP.

6. A system for transferring signals across a bus, said system comprising a plurality of line drivers, each of said line drivers comprising:

an circuitry for receiving an input signal having a first voltage swing between a first logic high level substantially equal to V_CC and a first logic low level substantially equal to V_SS, said input stage operating between a first high voltage rail having a voltage V_PP, wherein V_PP is greater than V_CC, and a low voltage rail having a voltage level of V_SS, wherein said circuitry for receiving outputs a boosted signal, said boosted signal having a second voltage swing between a second logic high level substantially equal to V_PP and a second logic low level substantially equal to V_SS ; and

an output stage operating between a second high voltage rail having a voltage level of V_CC and said low voltage rail for receiving said boosted signal from said circuitry for receiving, said output stage comprising;

a first N-channel transistor having a source coupled to a selected one of said plurality of lines and a drain coupled to said second high voltage rail; and

a second N-channel transistor having a drain coupled to said selected line and a source coupled to said low voltage rail.

7. The system as set forth in claim 6 wherein said voltage V_PP is greater than said voltage V_CC by at least a threshold voltage of said first N-channel transistor.

8. The system as set forth in claim 6 further comprising a power supply coupled to said first high voltage rail or generating said voltage V_PP.

9. The system as set forth in claim 8 wherein said power supply comprises:

a storage capacitor for storing a charge; and

a charge pump operating between said second high voltage rail and said low voltage rail for charging said storage capacitor to said voltage V_PP.

10. An integrated circuit for transmitting signals across a plurality of conductive lines, said integrated circuit comprising:

processing circuitry operating between a first high voltage rail having a voltage level of V_CC and a low voltage rail having a voltage level of V_SS, said processing circuitry generating a plurality of input signals having a first voltage swing between a first logic high level substantially equal to V_CC and a first logic low level substantially equal to V_SS ; and

a plurality of line drivers for receiving said plurality of input signals, said plurality of line drivers operating between a second high voltage rail having a voltage level of V_PP, wherein V_PP is greater than V_CC, and said low voltage rail, each of said line drivers comprising;

an circuitry for receiving a selected one of said input signals and outputting a boosted signal, said boosted signal having a second voltage swing between a second logic high level substantially equal to V_PP and a second logic low level substantially equal to V_SS ; and

an output stage operating between said first high voltage rail and said low voltage rail, said output stage comprising;

a first N-channel transistor having a source coupled to a select one of said plurality of lines and a drain coupled to said first high voltage rail; and

a second N-channel transistor having a drain coupled to said selected line and a source coupled to said low voltage rail.

11. The integrated circuit as set forth in claim 10 wherein said voltage V_PP, is greater than said voltage V_CC by at least a threshold voltage of said first N-channel transistor.

12. The integrated circuit as set forth in claim 10 further comprising a power supply coupled to said second high voltage rail for generating said voltage V_PP.

13. The integrated circuit as set forth in claim 12 wherein said power supply comprises:

a storage capacitor for storing a charge; and

a charge pump operating between said first high voltage rail and said low voltage rail for charging said storage capacitor to said voltage V_PP.

14. The integrated circuit as set forth in claim 12 wherein said power supply is disposed in an area of said integrated circuit remote from said plurality of line drivers.

15. An integrated circuit for transmitting signals across a plurality of conductive lines, said integrated circuit comprising:

a power source operating between a high voltage rail having a voltage level of V_CC and a low voltage rail having a voltage level of V_SS, said power source generating a voltage level of V_PP on an output of said power source, wherein V_PP is greater than V_CC ;

processing circuitry generating a plurality of data signals having a first voltage swing between a first logic high level substantially equal to V_CC and a first logic low level substantially equal to V_SS ; and

a plurality of level shifters, wherein each of said level shifters is coupled to said power source output and receives a selected one of said data signals, and wherein each of said level shifters generates a boosted drive signal having a second voltage swing between a second logic high level substantially equal to V_PP and a second logic low level substantially equal to V_SS.

16. The integrated circuit as set forth in claim 15 further comprising a plurality of output stages, each of said output stages receiving a selected one of said boosted drive signals and comprising:

a first N-channel transistor having a source coupled to a selected one of said plurality of conductive lines and a drain coupled to said high voltage rail; and

a second N-channel transistor having a drain coupled to said selected conductive line and a source coupled to said low voltage rail.

17. The integrated circuit as set forth in claim 16 wherein said voltage V_PP is greater than said voltage V_CC by at least a threshold voltage of said first N-channel transistor.

18. The integrated circuit as set forth in claim 17 wherein said charge pump comprises:

A second capacitor;

logic circuitry for controlling charging of said second capacitor in response to a clock signal;

a first transistor for selectively coupling said second capacitor to said high voltage rail;

a second transistor for selectively coupling said second capacitor with said storage capacitor; and

a third transistor for selectively coupling said storage capacitor to said high voltage rail.

19. The integrated circuit as set forth in claim 16 wherein said power source is disposed in an area of said integrated circuit remote from said plurality of buffers.