Direct digital to analog microwave frequency signal simulator

• US 5,764,087 A
• Filed: 06/07/1995
• Issued: 06/09/1998
• Est. Priority Date: 06/07/1995
• Status: Expired due to Fees

• Current Assignee: AAI Corporation (Textron Inc)
• Original Assignee: AAI Corporation (Textron Inc)
• Inventors: Clark, Charles John
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): LE, DINH THANH
• Application Number:
  US08/474,085
• Time in Patent Office: 1,098 Days
• Field of Search: 327/105, 327/106, 327/107, 327/100, 327/113, 327/114, 327/99, 327/144, 327/145, 327/119, 364/721
• US Class Current: 327/105
• CPC Class Codes: G06F 1/0335 the phase increment itself being a composed function of two or more variables, e.g. frequency and phase
• CPC Class Codes: H03B 21/01 by beating unmodulated signals of different frequencies

Abstract

A direct digital-to-analog microwave frequency signal synthesizer device which employs both wideband and narrowband direct digital frequency synthesizer (DDFS) circuitry to improve frequency and phase agility, reduce spurious performance, and minimize direct analog circuitry. A clock output having an extremely precise and highly stabilized frequency is fed to the wideband DDFS circuit and to the narrowband DDFS circuit. One or the other is selectively enabled by control logic circuitry. When the former is enabled, precision, high frequency resolution, low spurious, fast frequency switching is achieved at the microwave output. When the latter is enabled, precision, high frequency and phase resolution, low spurious, is achieved, providing frequency chirp, and frequency phase control at the microwave output. The output of the wideband DDFS circuit is processed to reduce the spurious response and up-converted, while the output of the narrow band DDFS circuit is directly up-converted. The selected DDFS circuit, is frequency up-converted to provide a synthesized microwave output signal.

Claims

1. An apparatus for direct digital-to-analog microwave for narrowband and wideband suppressed spurious frequency signal synthesis, comprising:

an oscillator for generating a fixed frequency output selected from a range of discrete frequencies;

a reference frequency generator connected to said oscillator for stabilizing the fixed frequency output;

a clock generator connected to said reference frequency generator for producing a clock output with a precise frequency governed by the reference frequency generator;

a wideband direct digital frequency synthesizer (DDFS) circuit connected to said clock generator for providing fast frequency switching output;

a narrowband DDFS circuit connected to said clock generator for providing a frequency chirp, phase controlled output;

a control logic circuit connected to both the wideband DDFS circuit and narrowband DDFS circuit to selectively enable the wideband DDFS circuit and narrowband DDFS circuit and thereby select from a pair of DDFS frequency outputs output respectively from said narrowband DDFS circuit and said wideband DDFS circuit;

a DDFS spurious reduction circuit connected to said wideband DDFS circuit for reducing spurious response of said frequency output; and

a microwave frequency converter circuit for expanding the frequency band and up-converting one of said selected DDFS frequency outputs to provide a synthesized microwave output signal therefrom.

2. The apparatus of claim 1, wherein said DDFS spurious reduction circuit comprises:

frequency generating means for providing multiple discrete frequencies;

upconversion and frequency expansion means, said upconversion and frequency expansion means accepting said multiple discrete frequencies for upconverting and expanding said input from said DDFS;

bandlimititing means for suppressing out of band harmonics and other out of band spurious from output of said upconversion and frequency expansion means, said bandlimiting means having an output;

frequency reduction means for bandlimiting said output of said bandlimiting means, said frequency reduction means selectively suppressing in band spurious, said frequency reduction means having an output; and

bandpass filtering means for accepting said output of said frequency reduction means and limiting extraneous out of band energy thereon.

3. The apparatus of claim 2, wherein said frequency reduction means constitutes a divide by N filter.

4. The apparatus of claim 3, wherein said frequency reduction means preferentially suppresses said in band spurious by 20 Log (N).

5. A method for direct digital-to-analog microwave frequency signal synthesis, comprising the steps of:

generating a clock output with a precise stabilized frequency;

outputting said clock output to a wide band direct digital frequency synthesizer (DDFS) circuit and to a narrow band DDFS circuit;

enabling selectively either said wide band DDFS circuit to provide a fast frequency switching output, or to said narrowband DDFS circuit to provide a frequency chirp, phase controlled output;

reducing in band spurious response of said enabled wide band DDFS circuit; and

microwave frequency converting the selected DDFS circuit frequency output respectively from said wide band DDFS circuit and said narrowband DDFS circuit to provide a synthesized microwave output signal therefrom.

6. The method for direct digital-to-analog microwave frequency signal synthesis of claim 5, wherein said step of reducing in band spurious response of said enabled wide band DDFS circuit comprises the steps of:

up converting an input from a DDFS thereby creating a signal;

frequency expanding said signal;

limiting the band width of said signal;

dividing by N said signal; and

limiting the band width of said signal to create an output signal, said output signal having suppressed in band spurious.