Variable delay circuit

• US 5,764,093 A
• Filed: 05/02/1997
• Issued: 06/09/1998
• Est. Priority Date: 11/28/1981
• Status: Expired due to Fees

• Current Assignee: Advantest Corporation
• Original Assignee: Advantest Corporation
• Inventors: Tsukahara, Hiroshi, Watanabe, Naoyoshi, Hayashi, Yokichi, Ochiai, Katsumi, Yamada, Masuhiro
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): ZWEIZIG, JEFFERY SHAWN
• Application Number:
  US08/850,816
• Time in Patent Office: 403 Days
• Field of Search: 327/264, 327/271, 327/272, 327/276, 327/277, 327/278, 326/82
• US Class Current: 327/276
• CPC Class Codes: H03K 2005/00071 by adding capacitance as a load
• CPC Class Codes: H03K 2005/00195 using FET's
• CPC Class Codes: H03K 2005/00234 using circuits having two logic levels
• CPC Class Codes: H03K 5/131 Digitally controlled
• CPC Class Codes: H03K 5/133 using a chain of active delay devices

Abstract

A fine variable delay circuit includes a buffer having an input connected to a signal input terminal and an output. The buffer has an output impedance and outputs a logical level from the output. The fine variable delay circuit also includes a schmidt trigger buffer having an input connected to the output of the buffer and an output connected to a signal output terminal, a CMOS transistor having a gate and two electrodes, the gate being connected to a connection point between said buffer and said schmidt trigger buffer. In addition, the fine variable delay circuit includes a first switching element connected between one of the electrodes of the CMOS transistor and one terminal of a power supply, a second switching element connected between another of the electrodes of the CMOS transistor and another terminal of the power supply, and a delay setting circuit responsive to a select signal for controlling the first switching element and the second switching element to set simultaneously each of the first switching element and the second switching element to one of an ON and an OFF state, thereby setting a delay.

Claims

1. A fine variable delay circuit comprising:

a buffer having an input connected to a signal input terminal receiving an input signal and an output, said buffer having an output impedance and outputting a logical level from the output;

a schmidt trigger buffer having an input connected to the output of said buffer and an output connected to a signal output terminal;

a CMOS transistor comprising a gate and two electrodes, said gate being connected to a connection point between said buffer and said schmidt trigger buffer;

a first switching element comprising one terminal connected to one of said electrodes of said CMOS transistor and another terminal connected to one terminal of a power supply;

a second switching element comprising one terminal connected to another of said electrodes of said CMOS transistor and another terminal connected to another terminal of said power supply; and

delay setting means responsive to a select signal for controlling said first switching element and said second switching element to set simultaneously each of said first switching element and said second switching element to one of an ON state and an OFF state,

whereby in said OFF state said CMOS transistor functions as a stray capacitance thereby providing a fixed delay, and in said ON state said CMOS transistor functions as an inverter thereby providing a fine delay in addition to said fixed delay.

2. The fine variable delay circuit according to claim 1, further comprising:

a second CMOS transistor having a gate and two electrodes, said gate being connected to the connection point between said buffer and said schmidt trigger buffer;

a third switching element connected between said one electrode of said second CMOS transistor and said one terminal of said power supply;

a fourth switching element connected between said other electrode of said CMOS transistor and said other terminal of said power supply; and

second delay setting means responsive to an another select signal for controlling said third and fourth switching elements to simultaneously set them to one of an ON state and an OFF state, thereby setting a delay.

3. The fine variable delay circuit according to claim 1, wherein said first and second switching elements are two FETs of different conductivity types.

4. The fine variable delay circuit according to claim 2, wherein said third and fourth switching elements are two FETs of different conductivity types.

5. The fine variable delay circuit according to claim 1, wherein said delay setting means comprises an inverter having an input connected to a select signal input terminal and an output connected to one of said first and second switching elements, said select signal input terminal being connected to the other of said first and second switching elements.

6. The fine variable delay circuit according to claim 2, wherein said second delay setting means comprises and inverter having an input connected to an another select signal input terminal and an output connected to one of said third and fourth switching elements, said other select signal input terminal being connected to the other of said third and fourth switching elements.

7. The fine variable delay circuit according to claim 2, wherein said second CMOS transistor comprises two parallel-connected CMOS transistors having construction and characteristics of the first CMOS transistor.