Automated method and system for designing an optimized integrated circuit
First Claim
1. An automated method for designing an integrated circuit, said method comprising:
- in response to receipt of a high-level functional description of an integrated circuit including both control logic and data flow logic, constructing an initial substrate layout of said integrated circuit, said initial substrate layout including a plurality of subcircuits electrically connected by a plurality of interconnects, wherein said initial substrate layout is constructed based upon estimated timing characteristics of said plurality of subcircuits;
arranging particular ones of said plurality of subcircuits to optimize performance of said substrate layout of said integrated circuit, wherein said arrangement of particular ones of said plurality of subcircuits is performed independently for subcircuits implementing control logic and subcircuits implementing data flow logic;
determining performance characteristics of said substrate layout, including timing characteristics of said plurality of subcircuits and resistive and capacitive characteristics of said plurality of interconnects;
in response to a determination of said performance characteristics of said substrate layout, adjusting operating power levels of selected subcircuits among said plurality of subcircuits and resistances of selected ones of said plurality of interconnects to optimize performance of said substrate layout, wherein said adjustment of operating power levels of said selected subcircuits is performed independently for subcircuits implementing control logic and subcircuits implementing data flow logic;
thereafter, repeating said step of determining performance characteristics of said substrate layout; and
in response to said repeated determination of said performance characteristics of said substrate layout, finalizing routing of said plurality of interconnects electrically connecting said plurality of subcircuits, wherein performance of said substrate layout of said integrated circuit is optimized by iteratively refining said initial substrate layout utilizing performance characteristic data.
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Abstract
An automated method and system for designing an integrated circuit are disclosed which construct an initial substrate layout of the integrated circuit in response to receipt of a high-level functional description of an integrated circuit. The initial substrate layout, which includes a number of subcircuits electrically connected by a number of interconnects, is constructed based upon estimated timing characteristics of the subcircuits. Next, particular subcircuits are arranged to optimize performance of the substrate layout of the integrated circuit. Performance characteristics of the substrate layout, including timing characteristics of the number of subcircuits and resistive and capacitive characteristics of the number of interconnects, are then determined. In response to a determination of the performance characteristics of the substrate layout, operating power levels of selected subcircuits and resistances of selected interconnects are adjusted to optimize performance of the substrate layout. Thereafter, the step of determining performance characteristics of the substrate layout is repeated. In response to the repeated determination of the performance characteristics of the substrate layout, routing of the number of interconnects electrically connecting the number of subcircuits is finalized. Thus, performance of the substrate layout of the integrated circuit is optimized by iteratively refining the initial substrate layout utilizing performance characteristic data.
68 Citations
24 Claims
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1. An automated method for designing an integrated circuit, said method comprising:
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in response to receipt of a high-level functional description of an integrated circuit including both control logic and data flow logic, constructing an initial substrate layout of said integrated circuit, said initial substrate layout including a plurality of subcircuits electrically connected by a plurality of interconnects, wherein said initial substrate layout is constructed based upon estimated timing characteristics of said plurality of subcircuits; arranging particular ones of said plurality of subcircuits to optimize performance of said substrate layout of said integrated circuit, wherein said arrangement of particular ones of said plurality of subcircuits is performed independently for subcircuits implementing control logic and subcircuits implementing data flow logic; determining performance characteristics of said substrate layout, including timing characteristics of said plurality of subcircuits and resistive and capacitive characteristics of said plurality of interconnects; in response to a determination of said performance characteristics of said substrate layout, adjusting operating power levels of selected subcircuits among said plurality of subcircuits and resistances of selected ones of said plurality of interconnects to optimize performance of said substrate layout, wherein said adjustment of operating power levels of said selected subcircuits is performed independently for subcircuits implementing control logic and subcircuits implementing data flow logic; thereafter, repeating said step of determining performance characteristics of said substrate layout; and in response to said repeated determination of said performance characteristics of said substrate layout, finalizing routing of said plurality of interconnects electrically connecting said plurality of subcircuits, wherein performance of said substrate layout of said integrated circuit is optimized by iteratively refining said initial substrate layout utilizing performance characteristic data. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An automated system for designing an integrated circuit, said system comprising:
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means for constructing an initial substrate layout of an integrated circuit in response to receipt of a high-level functional description of said integrated circuit including both control logic and data flow logic, said initial substrate layout including a plurality of subcircuits electrically connected by a plurality of interconnects, wherein said initial substrate layout is constructed based upon estimated timing characteristics of said plurality of subcircuits; means for arranging particular ones of said plurality of subcircuits to optimize performance of said substrate layout of said integrated circuit, wherein said means for arranging particular ones of said plurality of subcircuits operates on subcircuits implementing control logic independently of subcircuits implementing data flow logic; means for determining performance characteristics of said substrate layout, including timing characteristics of said plurality of subcircuits and resistive and capacitive characteristics of said plurality of interconnects; means for adjusting operating power levels of selected subcircuits among said plurality of subcircuits and resistances of selected ones of said plurality of interconnects to optimize performance of said substrate layout in response to a determination of said performance characteristics of said substrate layout, wherein said means for adjusting operating power levels of selected subcircuits operates on subcircuits implementing control logic independently of subcircuits implementing data flow logic; means for thereafter repeating said determination of performance characteristics of said substrate layout; and means for finalizing routing of said plurality of interconnects electrically connecting said plurality of subcircuits in response to said repeated determination of said performance characteristics of said substrate layout, wherein performance of said substrate layout of said integrated circuit is optimized by iteratively refining said initial substrate layout utilizing performance characteristic data. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A computer program product stored on a computer readable media for causing a data processing system to design an integrated circuit, said computer program product comprising:
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instruction means for causing said data processing system to construct an initial substrate layout of an integrated circuit in response to receipt of a high-level functional description of said integrated circuit including both control logic and data flow logic, said initial substrate layout including a plurality of subcircuits electrically connected by a plurality of interconnects, wherein said initial substrate layout is constructed based upon estimated timing characteristics of said plurality of subcircuits; instruction means for causing said data processing system to arrange particular ones of said plurality of subcircuits to optimize performance of said substrate layout of said integrated circuit, wherein said instruction means for causing said data processing system to arrange particular ones of said plurality of subcircuits operates on subcircuits implementing control logic independently of subcircuits implementing data flow logic; instruction means for causing said data processing system to determine performance characteristics of said substrate layout, including timing characteristics of said plurality of subcircuits and resistive and capacitive characteristics of said plurality of interconnects; instruction means for causing said data processing system to adjust operating power levels of selected subcircuits among said plurality of subcircuits and resistances of selected ones of said plurality of interconnects to optimize performance of said substrate layout in response to a determination of said performance characteristics of said substrate layout, wherein said instruction means for causing said data processing system to adjust operating lower levels of selected subcircuits among said plurality of subcircuits operates on subcircuits implementing control logic independently of subcircuits implementing data flow logic; instruction means for causing said data processing system to thereafter repeat said determination of performance characteristics of said substrate layout; and instruction means for causing said data processing system to finalize routing of said plurality of interconnects electrically connecting said plurality of subcircuits in response to said repeated determination of said performance characteristics of said substrate layout, wherein performance of said substrate layout of said integrated circuit is optimized by iteratively refining said initial substrate layout utilizing performance characteristic data. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24)
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Specification