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Memory circuit

  • US 5,764,588 A
  • Filed: 04/29/1997
  • Issued: 06/09/1998
  • Est. Priority Date: 04/30/1996
  • Status: Expired due to Fees
First Claim
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1. A memory circuit comprising:

  • a memory cell array in a matrix arrangement of a plurality of memory cells each having at least one read port;

    word lines each connected commonly to memory cells aligned in a row among the memory cells of the memory cell array; and

    bit lines each connected commonly to memory cells aligned in n rows (n≧

    2) among the memory cells of the memory cell array,current drivability of access transistors of memory cells sharing said n bit lines being set to satisfy the relation of 1;

    2;

    . . . ;

    2n-1.

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