Memory circuit

• US 5,764,588 A
• Filed: 04/29/1997
• Issued: 06/09/1998
• Est. Priority Date: 04/30/1996
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Hatori, Fumitoshi, Nogami, Kazutaka
• Primary Examiner(s): Nguyen, Tan T.
• Application Number:
  US08/848,223
• Time in Patent Office: 406 Days
• Field of Search: 365/230.05, 365/149, 365/150, 365/154, 365/185.03, 365/185.05, 365/189.04, 365/63, 365/72
• US Class Current: 365/230.05
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

A single-port memory or a multi-port memory with a higher density than conventional memory devices is realized, while using the same design rule, by decreasing the number of bit lines per column or port to decrease the space for wiring and the size of the entire memory. A memory circuit includes a memory cell array arranging a plurality of memory cells in a matrix, each memory cell having at least one read port; word lines each connected to memory cells aligned in a row among the memory cells of the memory cell array, and bit lines each connected to memory cells aligned in n rows (n≧2) among the memory cells of the memory cell array. Current drivability of access transistors of memory cells sharing n bit lines are set to satisfy the relation of 1:2: . . . :2^n-1. This results in decreasing the number of bit lines and the area of the memory.

Claims

1. A memory circuit comprising:

a memory cell array in a matrix arrangement of a plurality of memory cells each having at least one read port;

word lines each connected commonly to memory cells aligned in a row among the memory cells of the memory cell array; and

bit lines each connected commonly to memory cells aligned in n rows (n≧

2) among the memory cells of the memory cell array,

current drivability of access transistors of memory cells sharing said n bit lines being set to satisfy the relation of 1;

2;

. . . ;

2_n-1.

2. The memory circuit according to claim 1 further comprising current detecting sense amplifiers each connected to each said bit line to detect current values flowing in said bit line and to output n-bit date.

3. The memory circuit according to claim 1 wherein current drivability of said access transistors of 2 memory cells connected to at least one word line are different from each other.

4. The memory circuit according to claim 1 wherein threshold values of said access transistors of 2 memory cells connected to at least one of said word lines are different from each other.

5. The memory circuit according to claim 1 wherein said memory cells contain converter means for A/D-converting a current value of said bit line.

6. The memory circuit according to claim 1 wherein said memory cells contain switch means responsive to a control signal to selectively connect information hold means to said bit line.

7. A memory circuit comprising:

a memory cell array including a matrix arrangement of memory cells each having a plurality of read ports;

word lines each connected to memory cells aligned in each row among said memory cells of said memory cell array; and

bit lines each connected to memory cells aligned in each column among said memory cells of said memory cell array,

adjacent memory cells in a single column sharing a single bit line to which at least two of said read ports are connected, and current drivability of access transistors of n ports (n≧

2) sharing said bit line being set to satisfy the relation of 1;

2;

. . . ;

2^n-1.

8. The memory circuit according to claim 7 further comprising current detecting sense amplifiers each connected to each said bit line to detect values of currents flowing in said bit line and to output n-bit data.

9. A memory circuit comprising:

a memory cell array in a matrix arrangement of memory cells having m (m≧

2) columns and n (n≧

2) rows;

word lines to each of which m memory cells arranged in a row among said n rows being connected; and

at least one bit line to which at most one memory cell arranged in said n rows being connected;

a current detecting sense amplifier which identifies 2^m kinds of current values;

wherein a cell current value that flows in a memory cell in an m-numbered memory cell column is 2^m-1 times a cell current value that flows in a memory cell in a first memory cell column.

10. The memory circuit according to claim 9, wherein said current detecting sense amplifier connected to said bit line detects values of currents flowing in said bit line and outputs n-bit data.