Bit error rate detection system

• US 5,764,651 A
• Filed: 05/17/1996
• Issued: 06/09/1998
• Est. Priority Date: 05/17/1996
• Status: Expired due to Term

• Current Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Bullock, Dean C., Balakrishna, Sudhindar
• Primary Examiner(s): CHUNG, PHUNG M
• Application Number:
  US08/650,084
• Time in Patent Office: 753 Days
• Field of Search: 371/5.5, 371/5.1, 375/202, 375/222
• US Class Current: 714/708
• CPC Class Codes: H04J 2203/006 Fault tolerance and recovery
• CPC Class Codes: H04J 2203/0062 Testing
• CPC Class Codes: H04J 3/14 Monitoring arrangements for SDH/SONET rings H04J3/085
• CPC Class Codes: H04L 1/20 using signal quality detector
• CPC Class Codes: H04L 1/22 using redundant apparatus to increase reliability

Abstract

A system for determining a data stream using a variable length window for sampling of erred bits in the data stream is disclosed. A threshold maximum-allowable error rate is selected; a first window length to comprise a data stream sample is selected; the data stream is monitored for errors during the given window length; the allowable error is compared to the total number of errors detected during the monitoring step; and, if the detected error is greater than the allowable error, the window length is reduced and monitoring is continued using the reduced window length, else monitoring continues over successive window length periods. A signal degrade or signal fail condition signal is generated if the window length reaches zero. The system can be utilized to implement an automatic protection switching system for a SONET network.

Claims

1. A process, comprising the steps of:

(a) selecting an allowable bit threshold based on a bit error rate;

(b) selecting a window length comprising a number of frames over which a sample of the bit error rate will be compared;

(c) comparing an actual bit interleave parity for a frame t-1 with a calculated value of the error rate for the frame t-1;

(d) storing an error detected in the bit interleave parity; and

(e) comparing the number of stored errors detected in step (d) with the allowable bit threshold to determine an adjustment of the window length, said adjustment corresponding to changing said window length when the number of stored errors is different from the allowable error rate.

2. The process of claim 1, wherein changing said window length comprises

decreasing the window length if such errors exceed the allowable error rate;

and

increasing the window length if such errors do not exceed the allowable error rate.

3. The process of claim 1 wherein the process further includes the step of:

(f) generating a signal if the window length decreases below a selected minimum.

4. The process of claim 1 wherein said step (b) comprises the substeps of:

for each frame T, where T is an integer, calculating a bit interleave parity (BIP) for the frame, the bit interleave parity reflecting the bit error rate;

reading the BIP for a frame T-1 transmitted in the stored frame; and

comparing the calculated BIP for frame T-1 with an actually received BIP for frame T-1.

5. The process of claim 1 wherein said step (c) comprises:

adding the errors which result from the step of comparing to a cumulative error counter.

6. The process of claim 1 wherein said step (e) comprises:

querying a cumulative error register to determine if a cumulative number of errors equals the allowable threshold, and

if the cumulative number of errors exceeds the threshold, then increasing the window length, if not, then decreasing the window length.

7. The process of claim 6, wherein if the cumulative number of errors exceeds the threshold, said window length is increased by one.

8. A system for calculating the bit error rate of a data channel in a SONET network to enable automatic protection switching in accordance with the SONET specification, comprising:

establishing a threshold bit error rate and switch initiation time;

monitoring a data stream using a sliding window averaging calculation in which;

if the error rate is below the threshold bit error rate, the window length remains constant,

if the error rate increases above the threshold bit error rate, the window decreases in length such that the window decreases to zero if the error rate exceeds the threshold level for a time period equal to or less than the switch initiation time; and

generating a switch signal if the window length decreases to a minimum value.

9. The system of claim 8 wherein the step of monitoring comprises:

providing a denominator count register, a window length count register, a cumulative error register and a threshold register;

inputting a denominator count value into the denominator count register;

inputting an initial window count value into the window count register;

inputting a bit error threshold into the threshold register;

calculating for each frame T where T is an integer, a bit interleave parity (BIP) for frame T, the bit interleave parity reflecting the bit error rate;

reading the BIP for frame T-1 transmitted in frame T;

comparing, for a number of frames equalling the window length value multiplied by the denominator count value, the calculated BIP for frame T-1 with the BIP received for frame T-1;

adding the errors which result from the step of comparing to the cumulative error register;

querying the cumulative error register to determine if the cumulative number of errors equals the threshold register value;

if the cumulative number of errors exceeds the threshold, then increasing the window length register value, if not, then decreasing the window length register; and

generating an error signal if the window length equals zero.

10. The system of claim 9, wherein if the cumulative number of errors exceeds the threshold, said window length register value is increased by one.

11. A process for determining the bit error rate of a data stream within a time period, comprising:

(a) selecting an allowable error;

(b) selecting a sampling quantity of bits in the data stream;

(c) monitoring the data stream for errors during the sampling;

(d) comparing the allowable error to errors detected during the monitoring step; and

(e) if the errors detected are greater than the allowable error, reducing the sampling quantity of bits, else increasing the sampling quantity of bits and returning to step (b).

12. The process of claim 11 wherein said step (b) comprises selecting a window length based on an integer number of frames in the data stream.

13. The method of claim 12 wherein the step (b) comprises selecting a multiple and multiplying the window length by the multiple.

14. The process of claim 11 wherein the step of selecting comprises defining a window length multiplied by a multiple.

15. The process of claim 11 wherein said step (c) comprises:

calculating a bit interleave parity for a received frame; and

extracting a bit interleave parity for a previously-received frame from a received frame.

16. The process of claim 11 wherein said step (d) comprises:

storing the errors detected in said step (c); and

comparing said stored errors to a threshold error value.

17. The method of claim 11 wherein step (e) further comprises:

generating an error signal if the sampling quantity equals zero.

18. A process operable in a network element having a control processor and configurable memory, the process for determining the bit error rate in a SONET data stream, the data stream comprising a plurality of frames having a common frame length, comprising the steps of:

providing a denominator count register, a window length count register, a cumulative error register and a threshold register;

inputting a denominator count value into the denominator count register;

inputting an initial window count value into the window count register;

inputting a bit error threshold into the threshold register;

calculating for each frame T where T is an integer, a bit interleave parity (BIP) for frame T, the bit interleave parity reflecting the bit error rate;

reading the BIP for frame T-1 transmitted in frame T;

comparing, for a number of frames equalling the window length value multiplied by the denominator count value, the calculated BIP for frame T-1 with the actual received BIP for frame T-1;

adding the errors which result from the step of comparing to the cumulative error register;

querying the cumulative error register to determine if the cumulative number of errors equals the threshold register value;

if the cumulative number of errors exceeds the threshold, then increasing the window length register value, if not, then decreasing the window length register; and

generating an error signal if the window length equals zero.

19. The process of claim 18, wherein if the cumulative number of errors exceeds the threshold, said window length register value is increased by one.

20. A system memory coupled to a microprocessor, the memory including a plurality of memory registers and instructions for the microprocessor, the instructions comprising;

selecting an allowable bit error rate;

selecting a window length comprising a number of frames over which a sample of the bit error rate will be compared;

comparing an actual bit interleave parity for frame T-1 carried in frame T to a previously calculated value for the frame T-1;

storing any errors detected in the bit interleave parity between frames in a register;

at the end of the window, comparing errors accumulated to the allowable bit error rate and

if said errors accumulated exceed the allowable bit error rate, decreasing the window length;

or

if said errors accumulated do not exceed the allowable error rate, increasing the window length.

21. An automatic protection switching system for a SONET network, comprising:

a control processor;

a configurable memory operatively coupled to the control processor, having an integer multiple register, a window length register, a threshold register, and a cumulative error register configured therein;

a multiplexer, coupled to the control processor, the multiplexer having coupled thereto a plurality of optical carriers; and

program means for causing the processor to;

read a bit interleave parity for a frame T-1 transmitted in frame T;

window length value multiplied by a denominator count value, a bit interleave parity calculated for frame T-1 with a bit interleave parity received for frame T-1;

add the errors which result from the step of comparing to the cumulative error register;

query the cumulative error register to determine if a cumulative number of errors equals the threshold register value;

if the cumulative number of errors exceeds the threshold, then increase the window length register value, if not, then decrease the window length register; and

generate an error signal if the window length equals zero.

22. The automatic protection switching system of claim 21, wherein if the cumulative number of errors exceeds the threshold, said window length register value is increased by one.