Mobile demodulator architecture for a spread spectrum multiple access communication system

• US 5,764,687 A
• Filed: 06/20/1995
• Issued: 06/09/1998
• Est. Priority Date: 06/20/1995
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Easton, Kenneth D.
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): GLUCK, JEFFREY WILLIAM
• Application Number:
  US08/492,592
• Time in Patent Office: 1,085 Days
• Field of Search: 375/205, 375/206, 375/347, 375/349, 370/335, 370/342, 370/441, 370/479
• US Class Current: 375/147
• CPC Class Codes: H04B 1/7115 Constructive combining of multi-path signals, i.e. RAKE receivers
• CPC Class Codes: H04B 1/7117 Selection, re-selection, allocation or re-allocation of paths to fingers, e.g. timing offset control of allocated fingers

Abstract

The present invention involves demodulating a signal in a spread spectrum multiple access system employing a pilot on the forward link. The rake receiver separates the signal processing based on the period over which the processing occurs. Symbol rate processing is performed by a single time-shared multiply-accumulate datapath that services multiple finger front ends and a searcher front end. The front ends are dedicated circuits that perform all chip rate processing, producing a data vector and asserting a flag indicating the results are ready to be serviced by the shared datapath. A datapath controller arbitrates use of the datapath between the finger front ends, the searcher front end, and combining functions, configuring the datapath to service them on a first-come, first-serve basis. The controller sequences the datapath through a fixed routine as dictated by the signal processing associated with the block being serviced.

Claims

1. An integrated circuit for demodulating multiple instances of a spread spectrum signal over which symbols are transmitted at a symbol rate, wherein said symbols are divided into chips at a chip rate that is higher than the symbol rate comprising:

a plurality of demod front ends for demodulating the multiple instances of the spread spectrum signal at the chip rate; and

a symbol processing system for processing each demodulated instance of the spread spectrum signal at said symbol rate in a time-divided manner.

2. The integrated circuit as set forth in claim 1 wherein said symbol processing system is a digital signal processor.

3. The integrated circuit as set forth in claim 1 wherein,

said demod front ends are further for generating a corresponding set of symbol estimates by accumulating a set of chips associated with a symbol duration, and

said symbol processing system is further for phase rotating said set of symbol estimates, and combining said set of symbol estimates after phase rotation, wherein said symbol processing system operates on said set of symbol estimates in a time-divided manner.

4. The integrated circuit as set forth in claim 1 wherein a demod front end from said plurality of demod front ends is comprised of:

Walsh code demodulator for demodulating an instance of said spread spectrum signal with a Walsh code; and

spreading code demodulator for demodulating said Walsh-code-demodulated instance of said spread spectrum signal with a spreading code.

5. The integrated circuit of claim 1 wherein, said plurality of demod front ends contains more demod front ends than said symbol processing system contains symbol processing systems.

6. A spread spectrum demodulation apparatus for use in a multiple access communication system, the apparatus comprising:

a plurality of finger front ends, each front end receiving spread signals and performing chip rate signal processing associated with the spread spectrum demodulation apparatus;

a buffer, coupled to the plurality of finger front ends, for buffering per symbol accumulated data vectors;

a storage device for maintaining state information associated with symbol rate signal processing of the spread spectrum demodulation apparatus;

an arithmetic datapath, coupled to the storage device and the buffer, for performing symbol rate multiply and accumulate functions associated with signal processing of the spread spectrum demodulation apparatus, the arithmetic datapath having a symbol output; and

a datapath control circuit, coupled to the arithmetic datapath, for arbitrating the use of the arithmetic datapath among the plurality of finger front ends.

7. The spread spectrum demodulation apparatus of claim 6 wherein the arithmetic datapath comprises:

a first multiplexer having a first input coupled to the plurality of finger front ends and a second input coupled to the storage device, the first multiplexer selecting a first signal from a finger front end of the plurality of finger front ends or the storage device, the first multiplexer providing the first selected signal at an output;

a second multiplexer having a first input coupled to the plurality of finger front ends and a second input coupled to the storage device, the second multiplexer selecting a second signal from a finger front end of the plurality of finger front ends or the storage device, the second multiplexer providing the second selected signal at an output;

a multiplier having a first input coupled to the first multiplexer and a second input coupled to the second multiplexer, the multiplier providing a product signal at an output;

a third multiplexer having a first input coupled to the multiplier output and a second input coupled to the second multiplexer output, the third multiplexer providing either the second selected signal or the product signal at an output;

an adder/subtractor having a first input coupled to the third multiplexer output and a second input coupled to an arithmetic datapath output signal, the adder/subtractor providing a sum signal at an output;

a limiter/normalizer circuit, coupled to the adder/subtractor output, for selectively limiting the sum signal to a predetermined range, the limiter/ normalizer circuit providing a normalized sum signal; and

a latch, coupled to the limiter/normalizer circuit, for storing the normalized sum signal thus providing the arithmetic datapath output signal.

8. The spread spectrum demodulation apparatus of claim 6 and further including:

a searcher front end, coupled among the received spread signals and the arithmetic datapath, for calculating signal energy of the plurality of received spread signals; and

a symbol combiner, coupled to the arithmetic datapath, for combining the symbol output into a demodulated symbol stream.

9. The spread spectrum demodulation apparatus of claim 8 wherein the datapath control circuit further arbitrates the use of the arithmetic data path among the finger front ends, the searcher front end, and the symbol combiner.

10. The spread spectrum demodulation apparatus of claim 8 wherein the searcher front end comprises:

a pseudonoise sequence generator for generating an I sequence and a Q sequence;

a decimator, coupled to the received spread signals, for generating an I on-time signal, a Q on-time signal, an I late signal, and a Q late signal by selectively sampling the received spread signals;

a first despreader coupled to the I and Q sequences from the pseudonoise sequence generator and the I and Q on-time signals, the first despreader generating a first despread I signal and a first despread Q signal;

a second despreader coupled to the I and Q sequences from the pseudonoise signal generator and the I and Q late signals, the second despreader generating a second despread I signal and a second despread Q signal;

a plurality of accumulators, a first accumulator coupled to the first despread I signal, a second accumulator coupled to the first despread Q signal, a third accumulator coupled to the second despread I signal, and a fourth accumulator coupled to the second despread Q signal, the plurality of accumulators summing their respective I or Q signals;

a plurality of latches, each latch coupled to an accumulator of the plurality of accumulators; and

a timing generator for controlling the first and second despreaders, the pseudonoise sequence generator, and the plurality of accumulators.

11. The spread spectrum demodulation apparatus of claim 6 wherein each finger front end of the plurality of finger front ends comprises:

a pseudonoise sequence generator for generating an I sequence and a Q sequence;

a decimator, coupled to the received spread signals, for generating an I on-time signal, a Q on-time signal, an I late signal, and a Q late signal by selectively sampling the received spread signals;

a first despreader coupled to the I and Q sequences from the pseudonoise sequence generator and the I and Q on-time signals, the first despreader generating a first despread I signal and a first despread Q signal;

a second despreader coupled to the I and Q sequences from the pseudonoise signal generator and the I and Q late signals, the second despreader generating a second despread I signal and a second despread Q signal;

a Walsh sequence generator for generating a Walsh chip sequence;

an uncover circuit, coupled to the Walsh chip sequence generator, for reversing orthogonal covering of the first despread I and Q signals in response to the Walsh chip sequence;

a plurality of accumulators, a first accumulator coupled to the first despread I signal, a second accumulator coupled to the first despread Q signal, a third accumulator coupled to the second despread I signal, a fourth accumulator coupled to the second despread Q signal, and a fifth and sixth accumulator coupled to the uncover circuit, the plurality of accumulators summing their respective I or Q signals;

a plurality of latches, each latch coupled to an accumulator of the plurality of accumulators; and

a timing generator for controlling the first and second despreaders, the pseudonoise sequence generator, and the plurality of accumulators.

12. A method for spread spectrum demodulation in a multiple access communication system, the method comprising the steps of:

receiving spread signals by a plurality of finger front ends;

performing chip rate signal processing, associated with a spread spectrum demodulator, on the received spread signals;

buffering per symbol accumulated data vectors of the received spread signals;

saving state information, in a storage device, associated with symbol rate signal processing of the spread spectrum demodulator;

performing symbol rate multiplying and accumulating functions associated with signal processing of the finger front ends; and

arbitrating and sequencing the symbol rate multiplying and accumulating among the plurality of finger front ends.

13. The method of claim 12 wherein the step of arbitrating and sequencing further includes:

arbitrating among the plurality of finger front ends, a combiner, and a searcher front end;

performing searcher integration interval multiplying and accumulating functions associated with the signal processing of the searcher front end; and

performing the symbol rate accumulating functions associated with signal processing of the combiner.

14. The method of claim 12 wherein the step of performing symbol rate multiplying and accumulating includes the steps of:

multiplying a first signal from a finger front end of the plurality of finger front ends or the storage device with a second signal from a finger front end of the plurality of finger front ends or the storage device to produce a product signal;

adding the product signal or the second signal to a feedback signal to produce a sum signal; and

limiting the sum signal to a predetermined range to produce a limited sum signal;

normalizing the limited sum signal to produce a normalized signal; and

latching the normalized signal to produce the feedback signal.

15. The method of claim 14 and further including the step of latching the first signal and the second signal.

16. A radio for communicating in a multiple access communication system, the radio comprising:

a controller for controlling the radio;

a receiver for receiving a plurality of spread spectrum radio signals; and

a demodulator, coupled to the controller and the receiver, for demodulating the radio signal, the demodulator comprising;

a plurality of finger front ends, each front end receiving spread signals and performing chip rate signal processing associated with the spread spectrum demodulator;

a buffer, coupled to the plurality of finger front ends, for buffering per symbol accumulated data vectors;

a storage device for maintaining state information associated with symbol rate signal processing of the spread spectrum demodulator;

an arithmetic datapath, coupled to the storage device and the buffer, for performing symbol rate multiply and accumulate functions associated with signal processing of the spread spectrum demodulator, the arithmetic datapath having a symbol output;

a datapath control circuit, coupled to the arithmetic datapath, for arbitrating the use of the arithmetic datapath among the plurality of finger front ends;

a searcher front end, coupled among the plurality of received spread signals and the arithmetic datapath, for calculating signal energy of the received spread signals; and

a symbol combiner, coupled to the arithmetic datapath, for combining the symbol output into a demodulated symbol stream.

17. A method for spread spectrum demodulation in a multiple access communication system, the method comprising the steps of:

receiving spread signals by a plurality of finger front ends;

performing chip rate signal processing, associated with a spread spectrum demodulator, on the received spread signals;

buffering per symbol accumulated data vectors of the received spread signals;

saving state information associated with symbol rate signal processing of the spread spectrum demodulator;

performing symbol rate multiplying and accumulating functions associated with signal processing of the spread spectrum demodulator to provide a symbol output;

arbitrating and sequencing the symbol rate multiplying and accumulating among the plurality of finger front ends; and

combining the symbol output to generate a demodulated signal.