Latching inputs and enabling outputs on bidirectional pins with a phase locked loop (PLL) lock detect circuit
First Claim
1. A method of operating a semiconductor device having an input/output node comprising the steps of:
- storing an input signal appearing on the node using a control signal corresponding to a lock state of a phase locked loop (PLL);
delaying the control signal; and
,outputting an output signal on the node using the delayed control signal.
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Accused Products
Abstract
A circuit for latching inputs and enabling outputs on a bidirectional pin using a PLL lock detect circuit is disclosed. A PLL lock detect circuit generates an active lock control signal when an output reference signal is phase locked relative to an input reference signal applied to a phase locked loop (PLL) circuit. A latch and enable circuit is responsive to this lock control signal to latch the input signal (off of the pin), and, thereafter, enable output of an output signal onto the bidirectional pin. The latch and enable circuit includes a data latch to store the input signal when the lock control signal goes to an active state. The latch and enable circuit also includes a delay circuit to delay the lock control signal to produce a delayed lock control signal, and a tristateable output driver that is tristated when the delayed lock control signal is inactive, but, operates to pass (i.e., enable) the output signal to the bidirectional pin when the delayed lock control signal is active.
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Citations
19 Claims
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1. A method of operating a semiconductor device having an input/output node comprising the steps of:
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storing an input signal appearing on the node using a control signal corresponding to a lock state of a phase locked loop (PLL); delaying the control signal; and
,outputting an output signal on the node using the delayed control signal. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A circuit for latching an input signal and enabling an output signal on an input/output node of a semiconductor device comprising:
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means for storing said input signal appearing on said node using a control signal corresponding to a lock state of a phase locked loop (PLL); means for delaying said control signal to produce a delayed control signal; and
,means for enabling an output signal to be output on said node using said delayed control signal. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16)
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17. A circuit for latching an input signal and enabling an output signal on an input/output node of a semiconductor device comprising:
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a primary phase locked loop (PLL) lock detector for generating a primary lock signal corresponding to a lock state of a primary PLL; a data latch having a data input terminal for receiving said input signal from said node, an output terminal, and an enable input terminal responsive to said lock signal for controlling storage therein; a delay circuit having an input terminal responsive to said lock signal, and having an output terminal for producing a delayed lock signal; and
,a tristateable output driver having an input terminal for receiving said output signal and an output terminal for driving said output signal onto said input/output node, said driver further including an enable input terminal responsive to said delayed lock signal; wherein when said lock signal is generated in an active state, said latch stores said input signal therein for output on said data latch output terminal, said delayed lock signal being thereafter generated in an active state by said delay circuit to enable said driver to output said output signal to said input/output node. - View Dependent Claims (18, 19)
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Specification