Multi-byte processing of byte-based image data
First Claim
1. A method for processing image signals, comprising the steps of:
- (a) loading values representative of eight consecutive reference pixels into a register of eight 8-bit fields using a byte-based first SIMD instruction; and
(b) applying a second SIMD instruction to the register to transform the values, wherein the second SIMD instruction operates on the register as if the values were a single value, wherein the values are transformed by the steps of;
(1) subtracting four 16-bit values corresponding to eight consecutive target pixels from four 16-bit values in the register using a word-based SIMD subtraction instruction to generate four 16-bit differences;
(2) optionally shifting the four 16-bit differences left eight bits to generate four 16-bit shifted differences;
(3) squaring either the four 16-bit differences or the four 16-bit shifted differences to generate one or more 16-bit squares; and
(4) summing the 16-bit squares.
1 Assignment
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Accused Products
Abstract
Consecutive pixel values are loaded into the fields of a register. The data stored in the register is then transformed by operating on the register with one or more instructions that treat multiple pixel values as if they were single values. In a preferred embodiment, subsampled motion estimation processing is implemented on SIMD architecture. Values for consecutive pixels are loaded into the 8-bit fields of a SIMD register with a single byte-based SIMD load instruction. The contents of the register are then processed by applying one or more word-based SIMD instructions to the register which treat the data in the registers as 16-bit values. This word-based processing preferably results in sums of squares of differences between reference and target pixels used in motion estimation processing. Although the byte-based SIMD load instruction loads unwanted pixels (i.e., those pixels not selected for subsampled motion estimation processing) along with the desired pixels, the subsequent word-based SIMD processing treats the unwanted pixels as low-order bits of the desired pixels. The squares of differences may have errors, but the magnitudes of the errors are insignificant compared to the overall block comparison values and, as such, produce negligible if any affect on the selection of reference blocks during motion estimation processing.
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Citations
6 Claims
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1. A method for processing image signals, comprising the steps of:
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(a) loading values representative of eight consecutive reference pixels into a register of eight 8-bit fields using a byte-based first SIMD instruction; and (b) applying a second SIMD instruction to the register to transform the values, wherein the second SIMD instruction operates on the register as if the values were a single value, wherein the values are transformed by the steps of; (1) subtracting four 16-bit values corresponding to eight consecutive target pixels from four 16-bit values in the register using a word-based SIMD subtraction instruction to generate four 16-bit differences; (2) optionally shifting the four 16-bit differences left eight bits to generate four 16-bit shifted differences; (3) squaring either the four 16-bit differences or the four 16-bit shifted differences to generate one or more 16-bit squares; and (4) summing the 16-bit squares. - View Dependent Claims (2)
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3. An apparatus for processing image signals, comprising:
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(a) means for loading values representative of eight consecutive pixels into a register of eight 8-bit fields using a byte-based first SIMD instruction; and (b) means for applying a second SIMD instruction to the register to transform the values, wherein the second operation operates on the register as if two or more of the values were a single value, wherein means (b); (1) subtracts four 16-bit values corresponding to eight consecutive target pixels from four 16-bit values in the register using a word-based SIMD subtraction instruction to generate four 16-bit differences; (2) optionally shifts the four 16-bit differences left eight bits to generate four 16-bit shifted differences; (3) squares either the four 16-bit differences or the four 16-bit shifted differences to generate one or more 16-bit squares; and (4) sums the 16-bit squares. - View Dependent Claims (4)
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5. A storage medium having stored thereon machine-readable program code for processing image signals, wherein, when the program code is executed by a machine, the machine implements the steps of:
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(a) loading values representative of eight consecutive reference pixels into eight 8-bit fields of a register using a byte-based first SIMD instruction; and (b) applying a second SIMD instruction to the register to transform the values, wherein the second SIMD instruction operates on the register as if the values were a single value, wherein the values are transformed by the steps of; (1) subtracting four 16-bit values corresponding to eight consecutive target pixels from four 16-bit values in the register using a word-based SIMD subtraction instruction to generate four 16-bit differences; (2) optionally shifting the four 16-bit differences left eight bits to generate four 16-bit shifted differences; (3) squaring either the four 16-bit differences or the four 16-bit shifted differences to generate one or more 16-bit squares; and (4) summing the 16-bit squares. - View Dependent Claims (6)
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Specification
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- Resources
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Current AssigneeIntel Corporation
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Original AssigneeIntel Corporation
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InventorsNickerson, Brian R.
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Primary Examiner(s)CHANG, JON CARLTON
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Application NumberUS08/624,904Time in Patent Office804 DaysField of Search382/107, 382/236, 382/232, 382/304, 348/415, 348/416US Class Current382/107CPC Class CodesG06T 2207/10016 Video; Image sequenceG06T 7/238 using non-full search, e.g....
