High speed active bus

• US 5,764,935 A
• Filed: 11/23/1994
• Issued: 06/09/1998
• Est. Priority Date: 01/05/1990
• Status: Expired due to Term

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Bucher, Timothy, Bechtolsheim, Andreas, Kelly, Edmund
• Primary Examiner(s): Kulik, Paul V.
• Assistant Examiner(s): Von Buhr, Maria N.
• Application Number:
  US08/345,004
• Time in Patent Office: 1,294 Days
• Field of Search: 364/DIG. 1, 364/DIG. 2, 395/200, 395/325, 395/550, 395/700, 395/650, 395/725
• US Class Current: 710/110
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/4208 being a system bus, e.g. VME bus, Futurebus, Multibus

Abstract

A high speed bus structure which makes the bus effective and practical to use for both single processor and multiple processor environments. This is achieved by providing an active bus wherein a number of logic functions which control the operation of the bus are removed from the modules and are centralized and incorporated into the bus. The amount of bus functionality provided by the modules is minimized therefore decreasing the complexity and computational overhead of the modules and traffic on the bus that are attributable to supporting the functionality to operate the bus. The number of bussed signal lines is minimized by eliminating the bussed lines relevant to the centralized bus functions. In place of the bussed signal lines, dedicated signal lines connect the modules inserted into the bus and the bus components providing the centralized logic functions. Thus certain states or commands which were separate commands are now incorporated into one of the basic bus commands or communicated through dedicated signal lines which connect the centralized bus components and the modules. Furthermore, certain signal lines not considered to be directly related to system performance are eliminated and incorporated into a bus transaction.

Claims

1. An active high speed bus system comprising:

a first processor module;

a plurality of device modules;

a plurality of bussed signal lines coupled to said first processor module and said plurality of device modules, wherein said plurality of bussed signal lines include;

a first plurality of signal lines for transmitting address information in a first time frame and data in a second time frame;

a second plurality of signal lines for transmitting transaction specific information during said first time frame and data during said second time frame, said transaction specific information including information indicating a type of bus transaction;

a third plurality of signal lines for transmitting information indicating a status of a current bus transaction;

a plurality of bus components centralized as one unit separate and distinct from said first processor module and said plurality of device modules for providing centralized logic functions, said components including;

a component for arbitrating access to said bussed signal lines, said centralized arbiter component coupled to each of said plurality of device modules with one of a plurality of dedicated signal lines;

an interrupt handler component for selectively interrupting the use of said bussed signal lines, said interrupt handler component coupled to each of said plurality of device modules with one of a plurality of dedicated signal lines;

a system reset component for resetting said plurality of device modules, said system reset component coupled to each of said plurality of device modules with one of a plurality of dedicated signal lines;

a system clock component for providing clock signals to said plurality of device modules, said system clock component coupled to each of said plurality of device modules with one of a plurality of dedicated signal lines.

2. The active high speed bus system as provided in claim 1 wherein said transaction specific information includes information identifying a bus master device module to a bus slave device module.

3. The active high speed bus system as provided in claim 1 wherein said plurality of bus components for providing centralized logic functions further comprises an ID logic component for assigning ID'"'"'s to said plurality of device modules, said ID logic component coupled to each of said plurality of device modules with one of a plurality of dedicated signal lines.

4. The active high speed bus system as provided in claim 1 wherein said information indicating a status of a current bus transaction includes information separately, and distinctly indicating that:

the bus is idle and available for use by said plurality of device modules for a bus transaction;

a valid data transfer occurred from a bus master device module to a bus slave device module;

a bus error has occurred;

a time out has occurred;

an uncorrectable error has occurred;

a bus master device module should relinquish the bus and subsequently retry to gain access to the bus; and

a retry has occurred.

5. The active high speed bus system as provided in claim 1 wherein said information indicating a status of a current bus transaction includes:

information distinctly indicating that a first type of error has occurred, and information distinctly indicating that a second type of error has occurred, such that a plurality of error codes are provided and system overhead needed to determine and respond to error signals is decreased.

6. The active high speed bus system as provided in claim 1 wherein said transaction specific information includes:

access information asserted by a device module indicating that a current bus transaction requires privileged access, said privileged access being access to the bus that is requested by a system application and not by a user application.

7. The active high speed bus system as provided in claim 1 further comprising cache memory means coupled to the bus, and wherein said transaction specific information includes:

cache transaction information asserted by a device module indicating that a current bus transaction is cacheable in said cache memory means.

8. The active high speed bus system as provided in claim 1 further comprising:

a second processor module coupled to said plurality of bussed signal lines, and

wherein, said plurality of bussed signal lines further includes;

a fourth plurality of signal lines for transmitting information pertaining to a multiple processor environment.

9. A method for transferring data from a first module to a second module in a bus transaction in a computer system comprised of a plurality of modules selectively coupled to a bus and a centralized arbiter component and a centralized ID logic component, wherein said bus includes first, second, and third pluralities of bussed signal lines, and each of said modules is selectively coupled to said arbiter component with at least one dedicated signal line, and wherein each one of a plurality of said modules is selectively coupled to said ID logic component with dedicated ID signal line, said method comprising the steps of:

transmitting a bus request signal from said first module to said arbiter component over a first dedicated signal line;

transmitting a module identifier from said first module to said centralized ID logic component over said dedicated ID signal line for allowing the first module to be uniquely identified as a source of a bus transaction;

transmitting a bus grant signal from the arbiter component to said first module over a second dedicated signal line;

coupling from said first module to said second module address information over a first plurality of bussed signal lines during a first time frame;

coupling from said first module to said second module transaction specific information, including information indicating a type of bus transaction, over a second plurality of bussed signal lines during said first time frame;

coupling from said first module to said second module data over said first plurality of bussed signal lines and said second plurality of bussed signal lines during a second time frame.

10. The method for transferring data from a first module to a second module in a computer system as provided in claim 9 wherein said transaction specific information coupled from said first module to said second module over said second plurality of bussed signal lines further includes:

identification information duplicated from said ID signal line, identifying said first module to said second module.

11. The method for transferring data from a first module to a second module in a computer system as provided in claim 9 wherein said transaction specific information coupled from said first module to said second module over said second plurality of bussed signal lines further includes:

access information asserted by said first module, indicating that a bus transaction requires privileged access, said privileged access being access to the bus that is requested by a system application and not by a user application.

12. The method for transferring data from a first module to a second module in a computer system as provided in claim 9 wherein said computer system further comprises a virtually indexed memory cache and said method further includes the steps of:

coupling said address information from said first module to said second module over said first plurality of bussed signal lines; and

providing virtual address information for virtual addressing of said virtually indexed memory cache.

13. The method for transferring data from a first module to a second module in a computer system as provided in claim 9 wherein said computer system further comprises memory cache means, and said transaction specific information coupled from said first module to said second module over said second plurality of bussed signal lines further includes:

cache transaction information indicating that the data transfer is cacheable in said memory cache means.

14. The method for transferring data from a first module to a second module in a computer system as provided in claim 9 wherein said method further includes the step of:

coupling information indicating a status of the data transfer from said second module to said first module over a third plurality of bussed signal lines during said second time frame.

15. The method for transferring data from a first module to a second module in a computer system as provided in claim 9 wherein said method further includes the step of:

in the event of a data transfer error, coupling error information indicating a type of error from said second module to said first module over a third plurality of bussed signal lines during said second time frame.

16. The method for transferring data from a first module to a second module in a computer system as provided in claim 15, wherein said error information includes a plurality of different error statuses.

17. The method for transferring data from a first module to a second module in a computer system as provided in claim 16 wherein said plurality of different error statuses includes a bus error, a time-out, and an uncorrectible system error.

18. The method for transferring data from a first module to a second module in a computer system as provided in claim 9, wherein said transaction specific information coupled from said first module to said second module over said second plurality of bussed signal lines further includes:

data size information indicating to said second module the size of the data transfer.

19. The method for transferring data from a first module to a second module in a computer system as provided in claim 9, wherein said transaction specific information coupled from said first module to said second module over said second plurality of bussed signal lines further includes:

a bus lock indicator such that said first module is locked to said second module.