Shared memory device with arbitration to allow uninterrupted access to memory

• US 5,765,036 A
• Filed: 03/07/1997
• Issued: 06/09/1998
• Est. Priority Date: 10/06/1994
• Status: Expired due to Fees

• Current Assignee: Virtual Resource Communications, Inc.
• Original Assignee: Virtual Resource Communications, Inc.
• Inventors: Lim, Whai
• Primary Examiner(s): Swann, Tod R.
• Assistant Examiner(s): Thai, Tuan V.
• Application Number:
  US08/813,109
• Time in Patent Office: 459 Days
• Field of Search: 364/DIG. 1, 364/246.1, 395/474, 395/478, 395/481, 395/485
• US Class Current: 711/147
• CPC Class Codes: G06F 13/18 based on priority control G06F13/1605 takes precedence

Abstract

A shared memory system (10) is provided which interfaces with a shared memory bus (14). The shared memory bus (14) interfaces with a plurality of peripherals (12) through memory interfaces (16). Each of the memory interfaces (16) is operable to receive addresses from the associated one of the peripheral units (12) and communicate with the shared memory system (10) to process the addresses and subsequent data transfers in an ordered manner. The shared memory system (10) has associated therewith an arbitration logic circuit (78) that is operable to service bus requests from each of the memory interfaces (16). When a bus request is received, the requesting one of the memory interfaces (16) is allowed to access a single byte of data, after which it relinquishes the bus to another one of the memory interfaces (16). The previous requesting one of the buses that performed the one byte data transfer operation is then lowered in its priority such that all the requesting ones of the memory interfaces (16) are allowed to transfer at least one byte of data. This results in a byte-by-byte transfer of data without allowing any one of the memory interfaces (16) to seize and hold the bus for multiple data transfers in a sequential manner. In another mode, each of the memory interfaces (16) is allowed to seize the bus to continuously transfer data with a priority system implemented to allow a higher priority one to seize the bus away from the lower priority one.

Claims

1. A virtual media system, comprising:

a shared memory system having a plurality of storage locations, each storing data of a finite data size as a block of data that is accessible by an address, and when addressed, for storage of data therein or retrieval of data therefrom;

a memory access device for controlling access to said shared memory system;

a plurality of peripheral devices for accessing said shared memory system and generating addresses for addressing a memory location and transferring data thereto or retrieving data therefrom each of said peripheral devices having a memory space;

a plurality of memory interface devices, each associated with one of said peripheral devices and, each of said memory interface devices operable to interface between the one of said peripheral devices associated therewith and said shared memory system, each of said memory interface devices operable to receive said addresses for transfer to said shared memory system; and

an arbitration device associated with said shared memory system and said memory access device, said arbitration device for determining which of said peripheral devices is allowed to access said shared memory system through its associated one of said memory interface devices and operating on a block-by-block basis to allow each of said peripheral devices to only access said shared memory system for at least a block of data before relinquishing access thereto in response to a request from another one of said peripheral devices wherein all requesting ones of said memory interface devices will have uninterrupted access to a complete block of data prior to any of said memory interface devices having access to the next block of data;

said shared memory system having an address space that is different from the memory space of said peripheral devices and wherein each of said memory interface devices is operable to map the memory space of said associated peripheral device to the memory space of said shared memory system;

wherein each of said memory interface devices operates on a predetermined communication protocol between each of said memory interface devices and the associated one of said peripheral devices and wherein each of said memory interface devices has a communication interface module for effecting an interface between said associated peripheral device and the associated one of said memory interface device in accordance with said communication protocol; and

wherein each of said memory interface devices is afforded a predetermined priority and said arbitration device is operable to control access to said shared memory system in a second mode that is not on block-by-block basis, said second mode of operation operable to allow the highest priority one of said peripheral devices requesting access to said shared memory system to seize and maintain access to said shared memory system until all data access required thereby is complete and the access relinquished.

2. The virtual memory system of claim 1, wherein said block of data is a byte of data.

3. The shared memory system of claim 1, wherein each of said memory interface devices includes a central processing unit for providing processing capacity and a local memory, said local memory in each of said memory interface devices having a memory address space that is directly mapped to the memory space of said peripheral device associated with the respective associated one of said memory interface devices.