Method and apparatus for programming an array controller in a flash memory device

• US 5,765,184 A
• Filed: 09/27/1996
• Issued: 06/09/1998
• Est. Priority Date: 10/26/1993
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Durante, Richard Joseph
• Primary Examiner(s): Swann, Tod R.
• Assistant Examiner(s): Thai, Tuan V.
• Application Number:
  US08/720,311
• Time in Patent Office: 620 Days
• Field of Search: 365/185.29, 365/185.33, 365/189.05, 365/230.06, 395/428, 395/429, 395/430, 711/101, 711/102, 711/103
• US Class Current: 711/103
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators

Abstract

A flash memory device including programmable code store circuitry. The code store circuitry stores algorithms used by an array controller to erase and program a nonvolatile main memory array. The code store circuitry includes a nonvolatile instruction memory, which stores instructions. The code store circuitry also includes a number of support circuits, such as address decode circuitry, sense path circuitry, main array interface circuitry and several voltage generators. These circuits operate in several modes. In read mode, these support circuits ensure that the instruction data stored in the instruction memory is output to the array controller. In program and erase modes, the support circuits allow control of voltage level applied to the instruction memory and output of instruction to data to the user. In other words, these modes permit modification of the instruction memory. The support circuits are placed in the various modes via control signals output from control registers. Because these control registers are accessible to the device user, the user controls the mode in which the code store circuitry operates.

Claims

1. A memory array controller apparatus for accessing a main memory array, comprising:

programmable code store circuitry comprising;

a nonvolatile memory storing instructions for accessing the main memory array;

an address multiplexer for selecting addresses corresponding to instructions from one of the nonvolatile memory and an alternative source for execution in accordance with a mode of operation of the programmable code store circuitry; and

main array interface circuitry selectively coupled to one of the nonvolatile memory and the main memory for performing read, erase, and program operations, wherein the main array interface is coupled to access the main memory array in accordance with instructions from the nonvolatile memory during a read mode of the programmable code store circuitry, wherein the main array interface is coupled to permit modification of the nonvolatile memory in accordance with instructions from the alternative source during a non-read mode of the programmable code store circuitry.

2. The apparatus of claim 1 wherein the main memory array comprises nonvolatile memory.

3. The apparatus of claim 2, wherein the main memory array comprises flash memory.

4. The apparatus of claim 1 wherein the nonvolatile memory of the programmable code store circuitry comprises flash memory.

5. The apparatus of claim 1 wherein the alternative source is a page buffer.

6. The apparatus of claim 1 further comprising:

a user interface for providing addresses to the address multiplexer during the non-read mode of the programmable code store circuitry; and

a program counter for providing addresses to the address multiplexer during the read mode of the programmable code store circuitry.

7. A method of modifying array controller algorithms stored in a programmable code store circuitry for performing memory operations on a main memory array, comprising the steps of:

a) selecting an alternative source of instructions to provide erase instructions;

b) executing the erase instructions to erase a first set of instructions stored in the programmable code store circuitry;

c) selecting the alternative source of instructions to provide programming instructions;

d) providing at least one instruction from a second set of instructions; and

e) executing the programming instructions to store the at least one instruction in the programmable code store circuitry.

8. The method of claim 7 further comprising the step of:

f) repeating step e) for every instruction of the second set of instructions.

9. The method of claim 7 further comprising the step of:

f) writing the erase instructions to the alternative source, wherein the alternative source is a page buffer.

10. The method of claim 7 further comprising the step of:

f) writing the programming instructions to the alternative source, wherein the alternative source is a page buffer.

11. The method of claim 7 wherein the programmable code store circuitry comprises nonvolatile memory.

12. The method of claim 7 wherein the main memory array comprises nonvolatile memory.