Method and system for authentication of a memory unit for a computer system

• US 5,765,197 A
• Filed: 01/02/1996
• Issued: 06/09/1998
• Est. Priority Date: 12/16/1993
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Combs, James Lee
• Primary Examiner(s): Swann, Tod R.
• Assistant Examiner(s): Thai, Tuan V.
• Application Number:
  US08/581,859
• Time in Patent Office: 889 Days
• Field of Search: 364/DIG. 1, 364/DIG. 2, 380/4, 380/14, 380/20, 380/42, 395/186, 395/490, 395/427, 711/100, 711/163, 711/164
• US Class Current: 711/164
• CPC Class Codes: A63F 2300/201 Playing authorisation given at platform level
• CPC Class Codes: A63F 2300/206 Game information storage, e.g. cartridges, CD ROM's, DVD's, smart cards
• CPC Class Codes: G06F 12/1408 by using cryptography for digital transmission H04L9/00
• CPC Class Codes: G06F 21/10 Protecting distributed programs or content, e.g. vending or licensing of copyrighted material protection in video systems or pay television H04N7/16 ; Digital rights management [DRM]
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories
• CPC Class Codes: G06F 2207/7219 Countermeasures against side channel or fault attacks
• CPC Class Codes: G06F 2221/2109 Game systems
• CPC Class Codes: G06F 2221/2121 Chip on media, e.g. a disk or tape with a chip embedded in its case

Abstract

A computer system for high-performance video and audio manipulations comprising a locked memory cartridge and an audio/video/compact disk (CD) drive controller/coprocessor. The computer system has a central processing unit (CPU) with at least one bus associated therewith, with the bus having at least one bus line. The cartridge comprises a readable memory, a memory control circuit, a lock control circuit, and a connector all in circuit communication with each other. The connector allows the memory, the memory control circuit, and the lock control circuit to be pluggably connected in circuit communication with the CPU. The memory control circuit scrambles some of the bus lines, thereby scrambling the data in the memory on reset, and unscrambles the bus lines responsive to inputs from the lock control circuit. The lock control circuit monitors the bus, waiting for a proper combination of bus values to be asserted onto the bus, at which time the lock control circuit causes the memory control circuit to unscramble the bus lines. The audio/video/CD drive controller/coprocessor comprises a CPU interface, a CPU cache, a memory controller, a memory bus arbitrator, a DRAM refresher, a video controller, a CD drive controller, a digital signal processor (DSP) sound coprocessor, and a "blitter" graphics coprocessor in an integrated package.

Claims

1. A method of ensuring that a memory cartridge having a readable memory is authorized for use in a computer system having a central processing unit (CPU) in circuit communication with the readable memory via at least one bus having at least one bus line, said method comprising the steps of:

(a) scrambling said at least one bus line of said at least one bus to thereby create a scrambled bus;

(b) asserting an address on said scrambled bus;

(c) reading data associated with said asserted address on said scrambled bus;

(d) detecting a preselected set of events;

wherein said step of detecting includes the step of detecting a sequence of addresses asserted on said scrambled bus;

(e) unscrambling said at least one bus line of said at least one bus responsive to said detection of a preselected set of events to thereby create an unscrambled bus;

(f) asserting said address on said unscrambled bus;

(g) reading data associated with said asserted address on said unscrambled bus; and

(h) comparing said data associated with said asserted address on said scrambled bus to said data associated with said asserted address on said unscrambled bus.

2. The method of claim 1 where said step of detecting a preselected set of events includes the detection of at least one bus value asserted on said at least one bus.

3. The method of claim 1 wherein the step of scrambling said at least one bus line includes the step of switching said at least one bus line with a second bus line.

4. The method of claim 1 wherein the step of scrambling said at least one bus line includes the step of placing said address asserted on said at least one bus line on a plurality of bus lines.

5. The method of claim 1 wherein the step of scrambling said at least one bus line includes the step of randomly placing said address asserted on said at least one bus line on a plurality of bus lines.

13. The system or method of claim 1, 6, or 12 wherein one of said preselected events comprises a system power up.

14. The system or method of claim 1, 6, or 12 wherein one of said preselected events comprises a system reset.

15. The system or method of claim 1, 6 or 12 wherein one of said preselected set of events comprises at least one bus value asserted on said at least one bus.

6. An authentication system for determining whether a memory cartridge is authorized for use in a computer system, the authentication system comprising:

(a) a central processing unit (CPU) having at least one bus associated therewith, and wherein said at least one bus includes at least one bus line;

(b) an addressable memory cartridge in removable circuit communication with said CPU and having;

(1) a readable memory in circuit communication with said CPU;

(2) a bus line scrambler in circuit communication with said CPU and with said memory, interposed between said CPU and said memory along said one bus; and

(3) a lock control circuit in circuit communication with said CPU and said bus line scrambler;

(c) logic for comparing data associated with a scrambled address to data associated with an unscrambled address;

(d) logic for asserting an unscramble sequence code to said lock control circuit wherein said unscramble sequence code comprises a plurality of addresses having a predetermined order;

said lock control circuit configured such that said lock control circuit causes said bus line scrambler to scramble said at least one bus line of said at least one bus responsive to an occurrence of a first set of preselected events; and

said lock control circuit further configured such that said lock control circuit causes said bus line scrambler to cease scrambling said at least one bus line responsive to an occurrence of a second set of preselected events.

7. The bus line scrambler of claim 6 comprising logic for switching said at least one bus line with a second bus line.

8. The bus line scrambler of claim 6 comprising logic for placing an address asserted on said at least one bus line on a plurality of bus lines.

9. The bus line scrambler of claim 6 comprising logic for randomly placing an address asserted on said at least one bus line on a plurality of bus lines.

10. The bus line scrambler of claim 6 comprising a multiplexer.

11. The lock control circuit of claim 6 comprising a state machine having at least a lock state and an unlock state.

12. A system for authentication of a memory device, wherein the system comprises a CPU for executing instructions, at least one bus in circuit communication with said CPU and for transferring information to and from the CPU and an addressable memory cartridge in circuit communication with said CPU, said addressable memory cartridge comprising:

(a) a readable memory in circuit communication with said CPU;

(b) a bus line scrambler in circuit communication with said CPU and with said memory, interposed between said CPU and said memory along said one bus; and

(c) a lock control circuit in circuit communication with said CPU and said bus line scrambler;

said lock control circuit comprising;

(1) an address input for inputting a memory address into said lock control circuit;

(2) logic for detecting a preselected set of events in circuit communication with said address input;

(3) a scramble/unscramble output in circuit communication with said bus line scrambler and for controlling said bus line scrambler;

said scramble/unscramble output having a scramble state and an unscramble state; and

(4) a state machine for determining said state of said scramble/unscramble output;

said state machine responsive to said memory address input;

said state machine comprising;

(i) a locked state for causing said scramble/unscramble output to be in said scrambled state;

(ii) an intermediate locked state for causing said scramble/unscramble output to be in said scrambled state; and

(iii) an unlocked state for causing said scramble/unscramble output to be in said unscrambled state; and

wherein said system further comprises logic for comparing data in said scrambled state to data in said unscrambled state.

16. The system of claim 6 or 12 further comprising:

(a) an audio/video/CD drive controller/coprocessor in circuit communication with said CPU via said at least one bus; and

(b) a system memory in circuit communication with said audio/video/CD drive controller/coprocessor via a second bus;

(c) said audio/video/CD drive controller/coprocessor including an arbitrator for arbitrating control over said system bus, a memory interface, a graphics coprocessor, a digital signal processor, a compact disk controller, and a video controller all in circuit communication with said CPU and said system memory and each configured such that any one of said CPU, said graphics coprocessor, said digital signal processor, said compact disk controller, and said video controller may become bus master of said second bus.

17. The system of claim 6 or 12 further comprising:

(a) an audio/video/CD drive controller/coprocessor in circuit communication with said CPU via said at least one bus;

(b) a system memory in circuit communication with said audio/video/CD drive controller/coprocessor via a second system bus;

(c) said audio/video/CD drive controller/coprocessor including an arbitrator for arbitrating control over said second bus, a memory interface, a graphics coprocessor, a digital signal processor, a compact disk controller, and a video controller all in circuit communication with said CPU and said system memory and each configured such that any one of said CPU, said graphics coprocessor, said digital signal processor, said compact disk controller, and said video controller may become bus master of said second bus; and

(d) further comprising an interrupt controller for interfacing interrupts to said CPU and said arbitrator responsive to said interrupt controller such that said CPU does not have the highest priority for control over said second system bus until an interrupt occurs and is detected by said interrupt controller.