Memory control circuit that selectively performs address translation based on the value of a road start address

• US 5,765,212 A
• Filed: 07/28/1995
• Issued: 06/09/1998
• Est. Priority Date: 07/29/1994
• Status: Expired due to Fees

• Current Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Yamada, Susumu
• Primary Examiner(s): Chan, Eddie P.
• Assistant Examiner(s): KIM, HONG CHONG
• Application Number:
  US08/509,500
• Time in Patent Office: 1,047 Days
• Field of Search: 711/213, 711/204, 711/218, 711/217, 711/168, 711/169, 711/5, 711/157, 365/230.03, 365/230.04
• US Class Current: 711/213
• CPC Class Codes: G06F 12/04 Addressing variable-length words or parts of words
• CPC Class Codes: G06F 12/06 Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication G06F12/08 takes precedence
• CPC Class Codes: G11C 7/103 using serially addressed read-write data registers G11C7/1036 takes precedence
• CPC Class Codes: G11C 8/00 Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413

Abstract

A memory control circuit improves the read speed of a program memory stored in a ROM. The memory control circuit includes a memory divided into four blocks, an address translation circuit for providing address 4N+1 to blocks 0 and 1 only when the required read address is 4N+2 or 4N+3, a set of latch circuits for latching data read from each of the blocks, and a selector circuit for selecting necessary data from among the latched data and outputting it to a data bus. Accordingly, three or more blocks of memory are made readable in every latched operation.

Claims

1. A memory control circuit for controlling read and transfer of data from a memory in response to a read request by an instruction processing unit, comprising:

a memory divided into 2^M blocks i (i=0, 1, . . . , 2^M -1), each block i storing data corresponding to address 2^M N+i, where M is a natural number equal to or greater than 2, and N is a non-negative integer;

an address translation circuit for selectively performing address translation on a read address issued by the instruction processing unit in accordance with a predetermined translation rule, the address translation circuit receiving the read address and supplying output to blocks j (j=0, 1 , . . . , 2^M-1 -1) so that the read address is provided via the address translation circuit to the blocks j while the read address is directly provided to blocks k (k=2^M-1, 2^M-1 +1, . . . , 2^M -1);

a latch circuit provided for each block with one-to-one correspondence, each latch circuit latching data read from the corresponding block, the latching operation being carried out simultaneously for all of the blocks so as to allow 2^M blocks of memory including at least 2^M-1 +1 successive addresses to be readable by the instruction processing unit for every latching action; and

a selector circuit for selecting data among the latched data and outputting the selected data to a data bus, in response to an address and transfer timing output by the instruction processing unit,

wherein when the read start address requested by the instruction processing unit is 2^M N+j, the address translation circuit is not activated so that address 2^M N is supplied to all blocks, and

when the read start address requested by the instruction processing unit is 2^M N+k, the address translation circuit is activated to perform address translation so that address 2^M (N+1) is supplied to the blocks j, while address 2^M N is supplied to the blocks k.

2. The memory control circuit according to claim 1, wherein the instruction processing unit requests data-read of a maximum of 2^M-1 +1 successive addresses at one time.

3. The memory control circuit according to claim 2, wherein the instruction processing unit carries out a plurality of data transfers in a single cycle, the data being included in a single read operation.

4. The memory control circuit according to claim 3, wherein the instruction processing unit generates an address every one cycle unit, the generated address becoming a start address of data to be read in the next cycle.

5. The memory control circuit according to claim 3, wherein the simultaneous latching action of each latch circuit occurs only once a cycle after a predetermined time from the beginning of the cycle.

6. The memory control circuit according to claim 3, wherein the instruction processing unit generates 2^M-1 +1 read signals which correspond to data of the 2^M-1 +1 successive addresses.

7. The memory control circuit according to claim 6, wherein one of the read signals serves as a latch timing signal for the latch circuits.

8. The memory control circuit according to claim 3, wherein the instruction processing unit generates two read signals, one of the signals demanding first data read for each cycle, and the other of the signals demanding the subsequent data read.

9. The memory control circuit according to claim 8, wherein said one signal serves as a latch timing signal for the latch circuits.

10. The memory control circuit according to claim 1, wherein the read address is represented by address bits A₀ -A_n, and the address translation circuit is an adder for incrementing an address value represented by address bits A_M -A_n when the address bit A_M-1 has a value of "1".

11. An integrated circuit device incorporating the memory control circuit described in claim 1.

12. The integrated circuit device according to claim 11, wherein the integrated circuit device is a single-chip microcomputer.

13. A memory control circuit for controlling read and transfer of data from a memory in response to a read request by an instruction processing unit, the memory being divided into an even number of blocks greater than or equal to 4, said memory control circuit comprising:

an address translation circuit for selectively performing address translation on a read address issued by the instruction processing unit in accordance with a predetermined translation rule, the address translation circuit supplying output to the blocks of one half of the memory so that the read address is provided via the address translation circuit to the blocks of the one half of the memory, while the read address is directly provided to the blocks of the other half of the memory;

a plurality of latch circuits, each of the latch circuits being provided for one of the blocks of the memory to latch data read from the corresponding block, the latching operation being carried out simultaneously for all of the latch circuits so as to allow all blocks of the memory, including at least N successive addresses (where N=half the number of blocks+1), to be made readable by the instruction processing unit for every latching operation; and

a selector circuit for selecting data from the latched data for output to a data bus, the selector circuit operating in response to a timing signal from the instruction processing unit,

wherein when the read start address requested by the instruction processing unit corresponds to an address in one of the blocks of the one half of the memory, the address translation circuit is not activated so that the read address issued by the instruction processing unit is supplied to all blocks, and

when the read start address requested by the instruction processing unit corresponds to an address in one of the blocks of the other half of the memory, the address translation circuit is activated to perform address translation so that a translated read address is supplied to the blocks of the one half of the memory, while the read address issued by the instruction processing unit is supplied to the blocks of the other half of the memory.

14. The memory control circuit according to claim 13, wherein the instruction processing unit requests data-read of a maximum of N successive addresses at one time.

15. The memory control circuit according to claim 14, wherein the instruction processing unit carries out a plurality of data transfers in a single cycle, the data being included in a single read operation.

16. The memory control circuit according to claim 15, wherein the instruction processing unit generates an address every one cycle unit, the generated address becoming a start address of data to be read in the next cycle.

17. The memory control circuit according to claim 15, wherein the simultaneous latching action of the latch circuits occurs only once a cycle after a predetermined time from the beginning of the cycle.

18. The memory control circuit according to claim 13,

wherein the read address is represented by address bits A_0-An, and

the address translation circuit selectively increments the value of address bits A_M -A_n based on the value of address bits A₀ -A_M-1.