Data processor with an efficient bit move capability and method therefor

• US 5,765,216 A
• Filed: 06/17/1996
• Issued: 06/09/1998
• Est. Priority Date: 01/21/1994
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Astrachan, Paul M., Anderson, Donald C., Weng, Chia-Shiann, Kuenast, Walter U., Weng, Kenneth C., Curtis, Peter C.
• Primary Examiner(s): Lane, Jack A.
• Application Number:
  US08/665,927
• Time in Patent Office: 722 Days
• Field of Search: 711/214, 711/220, 395/898
• US Class Current: 711/214
• CPC Class Codes: G06F 9/30018 Bit or string instructions
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants

Abstract

A data processor (40) includes source (60) and destination (61) address generation units (AGUs) to update source and destination addresses for efficient digital signal processing (DSP) functions. The data processor (40) includes an instruction decoder (41) which recognizes a bit movement instruction, which is frequently encountered in data interleaving operations. In response to the bit movement instruction, the instruction decoder (41) causes the source (60) and destination (61) AGUs to update their present addresses using variable offset values. The instruction decoder (41) further causes a bus controller (44) to convert these bit addresses to corresponding operand addresses and bit fields. The bus controller (44) accesses source and destination operands using the operand addresses. The instruction decoder (41) then causes an execution unit (45) to transfer a bit from the source operand indicated by the source bit field to a bit position of the destination operand indicated by the destination bit field.

Claims

1. A data processor with an efficient bit move capability, comprising:

an instruction decoder having an input for receiving one of a plurality of instructions including a bit move instruction, and an output for providing first, second, and third decoded signals in response to said bit move instruction;

an address generator coupled to said instruction decoder, having source and destination portions thereof;

said source portion providing a present source address and updating said present source address according to a source offset, in response to said first decoded signal;

said destination portion providing a present destination address and updating said present destination address according to a destination offset, in response to said second decoded signal;

a bus controller having source and destination address inputs for receiving said present source and destination addresses, respectively, for calculating a source operand address and a source bit field from said present source address and a destination operand address and a destination bit field from said present destination address, in response to said third decoded signal; and

an execution unit coupled to source and destination data paths for receiving source and destination operands at addresses represented by said source and destination operand addresses, respectively, for moving a bit of said source operand selected by said source bit field into a bit position of said destination operand selected by said destination bit field, in response to said third decoded signal.

2. The data processor of claim 1 wherein said bus controller comprises:

a source address converter having an input for receiving said present source address, and an output for providing a converted source address, said source address converter dividing said present source address by a number of bits of said source operand to form said converted source address; and

a source multiplexer having a first input for receiving said present source address, a second input for receiving said converted source address, a control input for receiving said third decoded signal, and an output for providing said source operand address.

3. The data processor of claim 1 wherein said bus controller comprises:

a destination address converter having an input for receiving said present destination address, and an output for providing a converted destination address, said destination address converter dividing said present destination address by a number of bits of said destination operand to form said converted destination address; and

a destination multiplexer having a first input for receiving said present destination address, a second input for receiving said converted destination address, a control input for receiving said third decoded signal, and an output for providing said destination operand address.

4. The data processor of claim 1 wherein each of said source and destination operands are characterized as being byte operands, and wherein each of said source and destination operand addresses are byte addresses.

5. The data processor of claim 1 wherein said instruction decoder further provides said first and second decoded signals in response to predetermined ones of said plurality of instructions other than said bit move instruction.

6. The data processor of claim 1 wherein said address generator comprises an address generation unit (AGU), said source portion thereof being further responsive to a source modulus.

7. The data processor of claim 1 wherein said address generator comprises an address generation unit (AGU), said destination portion thereof being further responsive to a destination modulus.

8. A data processor with an efficient bit move capability, comprising:

decoding means for receiving one of a plurality of instructions including a bit move instruction, and for providing first, second, and third decoded signals in response to said bit move instruction;

source address generation means for providing a present source address and for updating said present source address according to a source offset, in response to said first decoded signal;

destination address generation means for providing a present destination address and for updating said present destination address according to a destination offset, in response to said second decoded signal;

bus access means for receiving said present source and destination addresses, for calculating a source operand address and a source bit field from said present source address and a destination operand address and a destination bit field from said present destination address, in response to said third decoded signal, and for fetching source and destination operands at locations indicated by said source operand address and said destination operand address, respectively; and

bit movement means coupled to said bus access means, for moving a bit of said source operand selected by said source bit field into a bit position of said destination operand selected by said destination bit field, in response to said third decoded signal.

9. The data processor of claim 8 wherein said bus access means comprises means for storing said destination operand including said bit position thereof selected by said destination bit field, at said destination operand address.

10. The data processor of claim 8 wherein said source address generation means further updates said present source address according to a source modulus.

11. The data processor of claim 8 wherein said destination address generation means further updates said present destination address according to a destination modulus.

12. A method for efficiently moving bits between operands in a data processor, comprising the steps of:

receiving a bit move instruction;

and in response to receiving said bit move instruction performing the steps of;

converting a present source address to a source operand address and a source bit field, wherein said present source address is a bit address;

converting a present destination address to a destination operand address and a destination bit field, wherein said present destination address is a bit address;

fetching a source operand from an address indicated by said source operand address;

fetching a destination operand from an address indicated by said destination operand address;

moving a bit of said source operand selected by said source bit field into a bit position of said destination operand selected by said destination bit field to provide an updated destination operand;

updating said present source address using a source offset; and

updating said present destination address using a destination offset.

13. The method of claim 12 wherein said step of converting said present source address to said source operand address and said source bit field comprises the step of converting said present source address to said source operand address by dividing said present source address by a number of bits in said source operand.

14. The method of claim 13 wherein said step of converting said present source address to said source operand address by dividing said present source address by said number of bits in said source operand, comprises the step of shifting said present source address by a predetermined number to obtain said source operand address, wherein said number of bits in said source operand is equal to two raised to a power of said predetermined number.

15. The method of claim 14 wherein said step of converting said present destination address to said destination operand address and said destination bit field comprises the step of converting said present destination address to said destination operand address by dividing said present destination address by a number of bits in said destination operand.

16. The method of claim 15 wherein said step of converting said present destination address to said destination operand address by dividing said present destination address by said number of bits in said destination operand, comprises the step of shifting said present destination address by a predetermined number to obtain said destination operand address, wherein said number of bits in said destination operand is equal to two raised to a power of said predetermined number.

17. The method of claim 12 further comprising the step of storing said updated destination operand at said destination operand address.

18. The method of claim 12 further comprising the step of simultaneously performing said steps of converting said present source address to said source operand address and said source bit field and converting said present destination address to said destination operand address and said destination bit field.

19. The method of claim 12 wherein said step of updating said present source address further comprises the step of updating said present source address using said source offset and a source modulus.

20. The method of claim 12 wherein said step of updating said present destination address further comprises the step of updating said present destination address using said destination offset and a destination modulus.

21. In a data processor having a source address generator for updating a source operand address according to a source base address and a source offset, and a destination address generator for updating a destination operand address according to a destination base address and a destination offset, a method of efficiently implementing a bit move operation, comprising the steps of:

receiving a bit move instruction; and

in response to receiving said bit move instruction performing the steps of;

providing source and destination bit addresses respectively to said source and destination address generators in response to the bit move instruction;

converting an output of said source address generator to a source operand address and a source bit field;

converting an output of said destination address generator to a destination operand address and a destination bit field;

fetching a source operand at an address indicated by said source operand address;

fetching a destination operand at an address indicated by said destination operand address; and

moving a bit of said source operand selected by said source fit field into a bit position of said destination operand selected by said destination bit field to provide an updated destination operand.

22. In a data processor for use with a memory which couples an operand to a data bus in response to receiving a corresponding address, wherein the operand includes a plurality of bits, a method for efficiently moving a bit from a source bit position in the memory to a destination bit position in the memory comprising the steps of:

receiving a bit move instruction which specifies a source bit address and a destination bit address;

and in response to receiving said bit move instruction, performing the steps of;

calculating a source operand address and a source offset using said source bit address;

calculating a destination operand address and a destination offset using said destination bit address;

fetching a source operand corresponding to said source bit address using said source operand address;

fetching a destination operand corresponding to said destination bit address using said destination operand address;

extracting the bit from said source operand using said source offset; and

inserting the bit into said destination operand using said destination offset.

23. The method of claim 22 further comprising the step of performing said step of calculating said source operand address and said source offset using a source address generation unit.

24. The method of claim 22 further comprising the step of performing said step of calculating said destination operand address and said destination offset using a destination address generation unit.