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Data processor with an efficient bit move capability and method therefor

  • US 5,765,216 A
  • Filed: 06/17/1996
  • Issued: 06/09/1998
  • Est. Priority Date: 01/21/1994
  • Status: Expired due to Term
First Claim
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1. A data processor with an efficient bit move capability, comprising:

  • an instruction decoder having an input for receiving one of a plurality of instructions including a bit move instruction, and an output for providing first, second, and third decoded signals in response to said bit move instruction;

    an address generator coupled to said instruction decoder, having source and destination portions thereof;

    said source portion providing a present source address and updating said present source address according to a source offset, in response to said first decoded signal;

    said destination portion providing a present destination address and updating said present destination address according to a destination offset, in response to said second decoded signal;

    a bus controller having source and destination address inputs for receiving said present source and destination addresses, respectively, for calculating a source operand address and a source bit field from said present source address and a destination operand address and a destination bit field from said present destination address, in response to said third decoded signal; and

    an execution unit coupled to source and destination data paths for receiving source and destination operands at addresses represented by said source and destination operand addresses, respectively, for moving a bit of said source operand selected by said source bit field into a bit position of said destination operand selected by said destination bit field, in response to said third decoded signal.

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