Power transistor device having ultra deep increased concentration region

• US 5,766,966 A
• Filed: 06/18/1996
• Issued: 06/16/1998
• Est. Priority Date: 02/09/1996
• Status: Expired due to Term

• Current Assignee: International Rectifier Corporation Japan Limited
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Ng, Chiu
• Primary Examiner(s): Niebling, John
• Assistant Examiner(s): LEBENTRITT, MICHAEL
• Application Number:
  US08/665,715
• Time in Patent Office: 728 Days
• Field of Search: 437/40, 437/41, 437/6, 148/DIG. 126
• US Class Current: 438/138
• CPC Class Codes: H01L 29/66333 Vertical insulated gate bipolar transistors
• CPC Class Codes: H01L 29/7393 Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: Y10S 148/126 Power FETs
• CPC Class Codes: Y10S 438/904 Charge carrier lifetime control

Abstract

A cellular insulated gate bipolar transistor ("IGBT") device employs increased concentration in the active region between spaced bases to a depth greater than the depth of the base regions. The implant dose which is the source of the increased concentration is about 3.5×10¹² atoms per centimeter squared and is driven for about 10 hours at 1175° C. Lifetime is reduced by an increased radiation dose to reduce switching loss without reducing breakdown voltage or increasing forward voltage, drop above previous levels. The increased concentration region permits a reduction in the spacing between bases and provides a region of low localized bipolar gain, increasing the device latch current. The avalanche energy which the device can successfully absorb while turning off an inductive load is significantly increased. The very deep increased conduction region is formed before the body and source regions in a novel process for making the new junction pattern.

Claims

1. A method of manufacture of a power semiconductor device comprising the steps of:

forming an oxide layer on a surface of a semiconductor chip which is of a first conductivity type;

forming a first window mask on a surface of said oxide layer, etching a portion of said oxide layer that is exposed by said first window mask to form thin oxide regions, applying carriers of said first conductivity type to said chip through said thin oxide regions and diffusing said carriers to a first depth into said substrate to form increased conduction regions;

the side boundaries of said increased conduction regions side diffusing toward one another to boundary positions which are at least close to one another;

forming a second window mask which overlies and is centered on the boundaries between said increased conduction regions and then applying a first given concentration of carriers of a second conductivity type to said chip surface through said second window mask;

forming a thin gate dielectric and a conductive gate electrode over at least portions of the surface of said increased conduction regions;

forming a third window mask which surrounds and is at least adjacent to the locations of respective ones of said second window mask and then applying a second given concentration of carriers of the second conductivity type, which is less than said first given concentration, to said chip through said third window mask;

diffusing said carriers of said first and second given concentrations of said second conductivity type to their final depths which are less than the final depth of said increased conduction regions of the first conductivity type, with said carriers of said first given concentration forming a body of high concentration and said carriers of said second given concentration forming a low concentration channel region which surrounds said body of high concentration and underlies said thin gate dielectric;

applying a high concentration of carriers of said first conductivity type through said third window mask and diffusing them to form shallow source regions which diffuse laterally to underlie said thin gate dielectric and bounds the inner edge of said low concentration channel region; and

forming a source electrode on said source regions and a drain electrode which is electrically connected to said chip.

2. The method of claim 1, wherein said oxide layer is formed to a thickness of about 1600 angstroms.

3. The method of claim 2, wherein each of said thin oxide regions has a thickness of about 800 angstroms.

4. The method of claim 1, wherein each of said thin oxide regions has a thickness of about 800 angstroms.

5. The method of claim 1, wherein the concentration in a segment of said increased conduction regions that is adjacent to the surface of said chip being at least twice that of a portion of said chip that is outside said boundary positions.

6. The method of claim 1, further comprising the step of forming a second oxide layer which becomes integral with said first oxide layer and said thin oxide regions, and wherein said step of forming a second window mask forms said second window mask atop said second oxide layer.

7. The method of claim 1, wherein the entire portion of said increased conduction regions that is located between respective pairs of said first and second given concentrations extends from said surface of said chip to a depth greater than the depth of said first and second given concentrations.

8. The method of claim 1, in which said carriers of said first type which are applied through said first window mask are diffused to a final depth which is reached by a diffusion of that concentration of carriers at about 1175°

C. for about 10 hours.

9. The method of claim 1, wherein said step of forming a third window mask includes forming said third window mask atop said thin gate dielectric and applying said second given concentration of carriers of the second conductivity type through said thin gate dielectric.

10. The method of claim 1, which includes the further step of reducing the lifetime of said semiconductor chip.

11. The method of claim 1, wherein said completed chip is thereafter exposed to an electron flux of greater than about 12 megarads.

12. The method of claim 1, wherein said completed chip is thereafter exposed to irradiation to kill lifetime.

13. The method of claim 1, which includes the further step of diffusing heavy metal atoms into said chip to kill lifetime.

14. A method of manufacture of a power semiconductor device comprising the steps of:

forming a first window mask on a surface of a semiconductor chip which is of a first conductivity type and applying carriers of said first conductivity type to the exposed surface of said chip through said first window mask and then diffusing said carriers to a first depth into said substrate to form increased conduction regions;

the side boundaries of said increased conduction regions side diffusing toward one another to boundary positions which are at least close to one another;

forming a second window mask which overlies and is centered on the boundaries between said increased conduction regions and then applying a first given concentration of carriers of a second conductivity type to said chip surface through said second window mask;

forming a thin gate dielectric and a conductive gate electrode over at least portions of the surface of said increased conduction regions;

forming, atop said thin gate dielectric, a third window mask which surrounds and is at least adjacent to the locations of respective ones of said second window mask and applying a second given concentration of carriers of the second conductivity type, which is less than said first given concentration, to said chip through said third window mask and through said thin gate dielectric;

diffusing said carriers of said first and second given concentrations of said second conductivity type to their final depths which are less than the final depth of said increased conduction regions of the first conductivity type, with said carriers of said first given concentration forming a body of high concentration and said carriers of said second given concentration forming a low concentration channel region which surrounds said body of high concentration and underlies said thin gate dielectric;

applying a high concentration of carriers of said first conductivity type through said third window mask and diffusing them to form shallow source regions which diffuse laterally to underlie said thin gate dielectric and bounds the inner edge of said low concentration channel region; and

forming a source electrode on said source regions and a drain electrode which is electrically connected to said chip.

15. The method of claim 14, wherein the concentration in a segment of said increased conduction regions that is adjacent to the surface of said chip being at least twice that of a portion of said chip that is outside said boundary positions.

16. The method of claim 14, wherein the entire portion of said increased conduction regions that is located between respective pairs of said first and second given concentrations extends from said surface of said chip to a depth greater than the depth of said first and second given concentrations.

17. The method of claim 14, in which said carriers of said first type which are applied through said first window mask are diffused to a final depth which is reached by a diffusion of that concentration of carriers at about 1175°

C. for about 10 hours.

18. The method of claim 14, which includes the further step of reducing the lifetime of said semiconductor chip.

19. The method of claim 14, wherein said completed chip is thereafter exposed to an electron flux of greater than about 12 megarads.

20. The method of claim 14, wherein said completed chip is thereafter exposed to irradiation to kill lifetime.

21. The method of claim 14, which includes the further step of diffusing heavy metal atoms into said chip to kill lifetime.