Multiple spacer formation/removal technique for forming a graded junction
First Claim
1. A method for forming a transistor, comprising:
- growing a gate dielectric upon a semiconductor substrate;
patterning a gate conductor between opposed sidewall surfaces across a portion of said dielectric;
forming a removable layer upon the sidewall surfaces of said gate conductor, wherein a portion of said removable layer formed upon the sidewall surfaces of said gate conductor comprises interior and exterior sidewall surfaces;
introducing a first concentration of dopants at a first energy into said semiconductor substrate at a first depth to form medium-doped-drain regions, wherein said medium-doped-drain regions have edges which are approximately aligned with the exterior sidewall surfaces of said removable layer;
forming spacers upon the exterior sidewalls of said removable layer, wherein said spacers comprise interior and exterior sidewall surfaces,implanting a second concentration of dopants at a second energy into said semiconductor substrate at a second depth to form source/drain regions, wherein said source/drain regions have edges aligned with the exterior sidewall surfaces of said spacers;
performing a thermal anneal at a first temperature to activate said first and second concentration of dopants;
removing said removable layer at least partially from the sidewall surfaces of said gate conductor;
introducing a third concentration of dopants at a third energy and at a third depth into said semiconductor substrate to form lightly-doped-drain regions, wherein said lightly-doped-drain regions have interior edges aligned with the sidewall surfaces of said gate conductor and exterior edges aligned with the interior sidewall surfaces of said spacers; and
performing a thermal anneal at a second temperature less than said first temperature to activate said third concentration of dopants.
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Accused Products
Abstract
A transistor and a transistor fabrication method are presented where a sequence of spacers are formed and partially removed upon sidewall surfaces of the gate conductor to produce a graded junction having a relatively smooth doping profile. The spacers include removable and non-removable structures formed on the sidewall surfaces. The adjacent structures have dissimilar etch characteristics compared to each other and compared to the gate conductor. A first dopant (MDD dopant) and a second dopant (source/drain dopant) are implanted into the semiconductor substrate after the respective formation of the removable structure and the non-removable structure. A third dopant (LDD dopant) is implanted into the semiconductor substrate after the removable layer is removed from between the gate conductor and the non-removable structure (spacer). As a result a graded junction is created having higher concentration regions formed outside of lightly concentration regions, relative to the channel area. Such a doping profile provides superior protection against the hot-carrier effect compared to the traditional LDD structure. The smoother the doping profile, the more gradual the voltage drop across the channel/drain junction. A more gradual voltage drop gives rise to a smaller electric field and reduces the hot-carrier effect. Furthermore, the MDD and source/drain implants are performed first, prior to the LDD implant. This allows high-temperature thermal anneals to be performed first, followed by lower temperature anneals second.
52 Citations
16 Claims
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1. A method for forming a transistor, comprising:
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growing a gate dielectric upon a semiconductor substrate; patterning a gate conductor between opposed sidewall surfaces across a portion of said dielectric; forming a removable layer upon the sidewall surfaces of said gate conductor, wherein a portion of said removable layer formed upon the sidewall surfaces of said gate conductor comprises interior and exterior sidewall surfaces; introducing a first concentration of dopants at a first energy into said semiconductor substrate at a first depth to form medium-doped-drain regions, wherein said medium-doped-drain regions have edges which are approximately aligned with the exterior sidewall surfaces of said removable layer; forming spacers upon the exterior sidewalls of said removable layer, wherein said spacers comprise interior and exterior sidewall surfaces, implanting a second concentration of dopants at a second energy into said semiconductor substrate at a second depth to form source/drain regions, wherein said source/drain regions have edges aligned with the exterior sidewall surfaces of said spacers; performing a thermal anneal at a first temperature to activate said first and second concentration of dopants; removing said removable layer at least partially from the sidewall surfaces of said gate conductor; introducing a third concentration of dopants at a third energy and at a third depth into said semiconductor substrate to form lightly-doped-drain regions, wherein said lightly-doped-drain regions have interior edges aligned with the sidewall surfaces of said gate conductor and exterior edges aligned with the interior sidewall surfaces of said spacers; and performing a thermal anneal at a second temperature less than said first temperature to activate said third concentration of dopants. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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Specification