Oxide strip that improves planarity

• US 5,766,971 A
• Filed: 12/13/1996
• Issued: 06/16/1998
• Est. Priority Date: 12/13/1996
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Bronner, Gary B., Natzle, Wesley C., Walton, Erick G., Ahlgren, David C., Yu, Chienfan
• Primary Examiner(s): DANG, TRUNG Q
• Application Number:
  US08/768,010
• Time in Patent Office: 550 Days
• Field of Search: 437/67, 437/72, 437/228 IS, 437/228 H, 216/39, 216/58, 148/DIG. 50
• US Class Current: 438/296
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: Y10S 148/05 Etch and refill

Abstract

A process for stripping thin layers of oxide such as sacrificial pad oxide employs etching chemistry that widens cracks to remove shallow cracks and limit the widening of deep cracks, thereby producing a final oxide surface on thick layers of oxide that is less rough than prior art methods and enabling the fabrication of oxide-filled trenches that have geometries and/or surface smoothness that were previously impossible.

Claims

1. A method of making an integrated circuit in a silicon substrate having a set of transistors formed in active areas of said substrate and interconnections therebetween, comprising the steps of:

preparing said substrate, including forming a pad oxide thereon;

etching at least one isolation trench about at least one active area;

filling said at least one isolation trench with fill oxide and removing excess fill oxide outside said at least one isolation trench, thereby forming a composite layer of oxide containing said pad oxide and said fill oxide meeting at at least one oxide interface having interface sidewalls;

etching said composite layer of oxide by reacting said composite layer of oxide with HF in a vacuum to form a first reaction product, said first reaction product containing a removal amount of Si, having a first volume, removed from said layer of oxide;

reacting said first reaction product with NH₃ in said vacuum to form a second reaction product in situ, said second reaction product having a second volume substantially greater than said first volume, said second reaction product also being substantially resistant to diffusion of HF, whereby said etching step is self-limiting;

continuing said step of reacting said oxide with HF until said pad oxide thickness is removed;

removing said second reaction product;

forming transistors in said active areas; and

interconnecting said transistors to form said integrated circuit.

2. A method according to claim 1, in which said fill oxide contains at least one defect having defect sidewalls, a defect bottom, an initial defect depth and an initial defect thickness, in which:

said step of forming said second reaction product in situ comprises forming said second reaction product on said defect sidewalls and said defect bottom until a reaction product thickness of said second reaction product blocks said defect, whereby said HF on said top surface reacts at a greater rate than said HF on said defect bottom so that said defect depth decreases.

3. A method according to claim 2, in which said reaction product thickness blocks said defect initially at said bottom of said defect, whereby said top surface etches at a faster rate than said defect bottom and a final defect shape has a final defect bottom width and a final defect top width greater than said final defect bottom width.

4. A method according to claim 3, in which said defect is a void having a void top within 30 nm of a top surface of said fill oxide.

5. A method according to claim 3, in which said defect is a seam in said fill oxide.

6. A method according to claim 3, in which said defect is a crack in said fill oxide.

7. A method according to claim 3, in which said defect is an interface between said fill oxide and a nitride liner in said isolation trench.

8. A method according to claim 1, in which said composite layer of oxide contains at least one step having an outer corner and in which said steps of reacting said oxide with HF and of reacting said first reaction product with NH₃ combine to attack said outer corner preferentially, thereby rounding said outer corner.

9. A method according to claim 1, in which said composite layer of oxide contains at least one step having an inner corner between said pad oxide and said fill oxide and in which said steps of reacting said oxide with HF and of reacting said first reaction product with NH₃ combine to inhibit attack on said inner corner.

10. A method of making an integrated circuit in a silicon substrate having a set of transistors formed in active areas of said substrate and interconnections therebetween, comprising the steps of:

preparing said substrate, including forming a pad oxide thereon;

etching at least one isolation trench about at least one active area having isolation sidewalls at an angle greater than 75°

;

filling said at least one isolation trench with fill oxide and removing excess fill oxide outside said at least one isolation trench, thereby forming a composite layer of oxide containing said pad oxide and said fill oxide meeting at at least one oxide interface having interface sidewalls;

etching said composite layer of oxide by reacting said composite layer of oxide with HF in a vacuum to form a first reaction product, said first reaction product containing a removal amount of Si, having a first volume, removed from said layer of oxide;

reacting said first reaction product with NH₃ in said vacuum to form a second reaction product in situ, said second reaction product having a second volume substantially greater than said first volume, said

second reaction product also being substantially resistant to diffusion of HF, whereby said etching step is self-limiting;

continuing said step of reacting said oxide with HF until said pad oxide thickness is removed;

removing said second reaction product;

forming transistors in said active areas; and

interconnecting said transistors to form said integrated circuit.

11. A method according to claim 10, in which said composite layer of oxide contains at least one step having an outer corner and in which said steps of reacting said oxide with HF and of reacting said first reaction product with NH₃ combine to attack said outer corner preferentially, thereby rounding said outer corner.

12. A method according to claim 10, in which said composite layer of oxide contains at least one step having an inner corner between said pad oxide and said fill oxide and in which said steps of reacting said oxide with HF and of reacting said first reaction product with NH₃ combine to inhibit attack on said inner corner.

13. A method according to claim 10, in which said fill oxide contains at least one defect having a defect top within 30 nm of a top surface of said fill oxide, defect sidewalls, a defect bottom, an initial defect depth and an initial defect thickness, and in which:

said step of forming said second reaction product in situ comprises forming said second reaction product on said defect sidewalls and said defect bottom until a reaction product thickness of said second reaction product blocks said defect, whereby said HF on said top surface reacts at a greater rate than said HF on said defect bottom so that said defect depth decreases.

14. A method of making an integrated circuit in a silicon substrate having a set of transistors formed in active areas of said substrate and interconnections therebetween, comprising the steps of:

preparing said substrate, including forming a pad oxide thereon;

etching at least one isolation trench about at least one active area;

filling said at least one isolation trench with fill oxide and removing excess fill oxide outside said at least one isolation trench, thereby forming a composite layer of oxide containing said pad oxide and said fill oxide meeting at least one oxide interface having interface sidewalls;

etching said composite layer of oxide by reacting said composite layer of oxide with HF in a vacuum to form a first reaction product, said first reaction product containing a removal amount of Si, having a first volume, removed from said layer of oxide;

reacting said first reaction product with NH₃ in said vacuum to form a second reaction product in situ, said second reaction product having a second volume substantially greater than said first volume, said second reaction product also being substantially resistant to diffusion of HF, whereby said etching step is self-limiting;

continuing said step of reacting said oxide with HF until said pad oxide thickness is removed and removing said second reaction product;

forming transistors in said active areas;

depositing at least one layer of interlevel oxide insulation above said transistors, said interlevel oxide having a having an interlevel oxide top surface and an initial interlevel oxide thickness and containing at least one defect having defect sidewalls, a defect bottom, an initial defect depth and an initial defect thickness;

reacting said interlevel oxide with HF in a vacuum to form a first reaction product, said first reaction product having a first interlevel volume, removed from said layer of interlevel oxide;

reacting said first reaction product with NH₃ in said vacuum to form a second reaction product in situ, said second reaction product having a second interlevel volume substantially greater than said first interlevel volume, said second reaction product also being substantially resistant to diffusion of HF, whereby said method of etching is self-limiting;

forming said second reaction product in situ on said defect sidewalls and said defect bottom until a reaction product thickness of said second reaction product blocks said defect, whereby said HF on said interlevel top surface reacts at a greater rate than said HF on said defect bottom so that said defect depth decreases;

continuing said step of reacting said interlevel oxide with HF until a removal amount of said interlevel oxide is removed; and

removing said second reaction product, whereby said defect has a final defect depth that is less than said initial defect depth; and

interconnecting said transistors to form said integrated circuit.

15. A method according to claim 14, in which said interlevel oxide contains at least one defect having defect sidewalls, a defect bottom, an initial defect depth and an initial defect thickness, in which:

said step of forming said second reaction product in situ comprises forming said second reaction product on said defect sidewalls and said defect bottom until a reaction product thickness of said second reaction product blocks said defect, whereby said HF on said interlevel top surface reacts at a greater rate than said HF on said defect bottom so that said defect depth decreases.

16. A method according to claim 15, in which said reaction product thickness blocks said defect initially at said bottom of said defect, whereby said top surface etches at a faster rate than said defect bottom and a final defect shape has a final defect bottom width and a final defect top width greater than said final defect bottom width.

17. A method according to claim 16, in which said defect is a void having a void top within 30 nm of a top surface of said fill oxide.

18. A method according to claim 16, in which said defect is a crack in said fill oxide.

19. A method according to claim 16, in which said defect is a seam in said fill oxide.

20. A method of etching a layer of oxide on a semiconductor wafer, said oxide having a top surface and an initial oxide thickness and containing at least one defect having defect sidewalls, a defect bottom, an initial defect depth and an initial defect thickness, comprising the steps of:

reacting said oxide with HF in a vacuum to form a first reaction product, said first reaction product containing a removal amount of Si, having a first volume, removed from said layer of oxide;

reacting said first reaction product with NH₃ in said vacuum to form a second reaction product in situ, said second reaction product having a second volume substantially greater than said first volume, said second reaction product also being substantially resistant to diffusion of HF, whereby said method of etching is self-limiting;

forming said second reaction product in situ on said defect sidewalls and said defect bottom until a reaction product thickness of said second reaction product blocks said defect, whereby said HF on said top surface reacts at a greater rate than said HF on said defect bottom so that said defect depth decreases;

continuing said step of reacting said oxide with HF until a removal amount of said initial oxide thickness is removed; and

removing said second reaction product, whereby said defect has a final defect depth that is less than said initial defect depth.

21. The method according to claim 20, in which said reaction product thickness blocks said defect initially at said bottom of said defect, whereby said top surface etches at a faster rate than said defect bottom and a final defect shape has a final defect bottom width and a final defect top width greater than said final defect bottom width.

22. A method according to claim 21, in which said layer of oxide contains a first area of deposited oxide and a second area of thermal oxide over an active region of said wafer, said deposited oxide and said thermal oxide meeting at least one defect comprising an oxide interface between said thermal oxide and said deposited oxide.

23. A method according to claim 21, in which said layer of oxide contains at least one step having an outer corner and in which said steps of reacting said oxide with HF and of reacting said first reaction product with NH₃ combine to attack said outer corner preferentially, thereby rounding said outer corner.

24. A method according to claim 21, in which said layer of oxide contains at least one step having an inner corner between said thermal oxide and said deposited oxide and in which said steps of reacting said oxide with HF and of reacting said first reaction product with NH₃ combine to inhibit attack on said inner corner.

25. A method of etching a layer of first material on a semiconductor wafer, said first material having a top surface and an initial first material thickness and containing at least one defect having defect sidewalls, a defect bottom, an initial defect depth and an initial defect thickness, comprising the steps of:

reacting said first material with at least one reactant in a vacuum to form a reaction product, said reaction product containing a removal volume of Si, and having a reaction product volume substantially greater than said removal volume, said reaction product also being substantially resistant to diffusion of HF, whereby said method of etching is self-limiting;

forming said reaction product in situ on said defect sidewalls and said defect bottom until a reaction product thickness of said reaction product blocks said defect, whereby said HF on said top surface reacts at a greater rate than said HF on said defect bottom so that said defect depth decreases;

continuing said step of reacting said first material with HF until a removal amount of said initial first material thickness is removed; and

removing said reaction product, whereby said defect has a final defect depth that is less than said initial defect depth.

26. The method according to claim 25, in which said reaction product thickness blocks said defect initially at said bottom of said defect, whereby said top surface etches at a faster rate than said defect bottom and a final defect shape has a final defect bottom width and a final defect top width greater than said final defect bottom width.