Method of making a dielectric structure for facilitating overetching of metal without damage to inter-level dielectric

• US 5,766,974 A
• Filed: 06/06/1996
• Issued: 06/16/1998
• Est. Priority Date: 12/23/1993
• Status: Expired due to Term

• Current Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Original Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Inventors: Ricco, Bruno, Sardella, John C.
• Primary Examiner(s): Bowers, Jr., Charles L.
• Assistant Examiner(s): GURLEY, LYNNE ANN
• Application Number:
  US08/659,558
• Time in Patent Office: 740 Days
• Field of Search: 437/195, 437/190, 437/194, 437/241, 437/DIG. 978, 216/102, 156/643.1, 156/646.1
• US Class Current: 438/624
• CPC Class Codes: H01L 21/32135 by vapour etching only
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Integrated circuit fabrication with a thin layer of oxynitride atop the interlevel dielectric, to provide an etch stop to withstand the overetch of the metal layer.

Claims

1. A method for fabricating integrated circuits, comprising the steps of:

(a) providing an integrated circuit structure on which transistors have been fabricated;

(b) depositing an interlevel dielectric layer, essentially comprising silicate glass, over said transistors;

(c) depositing a layer of silicon oxynitride over said interlevel dielectric layer;

(d) etching contact holes into said silicon oxynitride and interlevel dielectric layers, to expose portions of said transistors for electrical connection;

(e) depositing a layer of metal over said silicon oxynitride layer; and

(f) etching said metal layer with a plasma etch chemistry which includes chlorine, wherein said silicon oxynitride layer is etched by said plasma etch chemistry more slowly than said dielectric lever and said dielectric layer etched by said plasma etch chemistry more slowly than said metal layer; and

(g) continuing said etching step for more than 175% of the time required to clear said metal layer from flat surfaces;

whereby said silicon oxynitride layer protects said interlevel dielectric from erosion by said metal etching step.

2. The method of claim 1, wherein said interlevel dielectric comprises a doped silicate glass over an undoped silicate glass.

3. The method of claim 1, wherein said interlevel dielectric comprises at least two layers.

4. The method of claim 1, wherein said interlevel dielectric comprises borophosphosilicate glass.

5. The method of claim 1, wherein said interlevel dielectric is reflowed prior to deposition of said silicon oxynitride layer.

6. The method of claim 1, wherein said silicon oxynitride layer consists of silicon oxynitride having a refractive index of 175.

7. The method of claim 1, wherein the ratio of the as-deposited thickness of said metal layer to the as-deposited thickness of said silicon oxynitride layer is in the range between 5:

1 and 10;

1.

8. The method of claim 7, wherein said silicon oxynitride layer is deposited to an initial thickness of about 800 Å

.

9. The method of claim 1, wherein said metal layer is deposited to an initial thickness in the range between about 3000 Å

and about 6000 Å

inclusive.

10. The method of claim 1, wherein said metal layer comprises an alloy of aluminum.

11. The method of claim 1, wherein said metal layer comprises an alloy of aluminum over a barrier layer comprising at least 40% of titanium.

12. The method of claim 1, wherein said metal layer comprises a multilayer structure.

13. The method of claim 1, wherein said interlevel dielectric is further treated, after said step of etching contact holes, to smooth the uppermost portions of said contact holes.

14. The method of claim 1, wherein said interlevel dielectric has a total thickness in the range of 3000-10,000 Å

inclusive.

15. The method of claim 1, wherein said silicon oxynitride layer is deposited to an initial thickness in the range of 500-1000 Å

.

16. A method for fabricating integrated circuits, comprising the steps of:

(a) providing an integrated circuit structure on which transistors have been fabricated;

(b) depositing an interlevel dielectric layer comprising a silicate glass over said transistors;

(c) depositing an insulating etch stop layer over said interlevel dielectric layer;

(d) etching contact holes into said etch stop and interlevel dielectric layers, to expose portions of said transistors for electrical connection;

(e) depositing a layer of metal over said etch stop; and

(f) etching said metal layer with a plasma etch chemistry which etches the material of said etch stop layer more slowly than the material of said interlevel dielectric and more slowly than the material of said metal layer, and which etches said dielectric layer more slowly than the material of said metal layer; and

(g) continuing said etching step for more than 175% of the time required to clear said metal layer from flat surfaces;

whereby said etch stop layer protects said interlevel dielectric from erosion by said metal etching step.

17. The method of claim 16, wherein said interlevel dielectric comprises a doped silicate glass over an undoped silicate glass.

18. The method of claim 16, wherein said interlevel dielectric comprises at least two layers.

19. The method of claim 16, wherein said interlevel dielectric comprises borophosphosilicate glass.

20. The method of claim 16, wherein said interlevel dielectric is reflowed prior to deposition of said etch stop layer.

21. The method of claim 16, wherein said etch stop layer consists of silicon oxynitride having a refractive index of 1.75.

22. The method of claim 16, wherein the ratio of the as-deposited thickness of said metal layer to the as-deposited thickness of said etch stop layer is in the range between 5:

1 and 10;

1.

23. The method of claim 22, wherein said etch stop layer is deposited to an initial thickness of about 800 Å

.

24. The method of claim 16, wherein said metal layer is deposited to an initial thickness in the range between about 3000 Å

and about 6000 Å

inclusive.

25. The method of claim 16, wherein said metal layer comprises a multilayer structure.

26. The method of claim 16, wherein said interlevel dielectric is further treated, after said step of etching contact holes, to smooth the uppermost portions of said contact holes.

27. The method of claim 16, wherein said interlevel dielectric has a total thickness in the range of 3000-10,000 Å

inclusive.

28. The method of claim 16, wherein said etch stop layer is deposited to an initial thickness in the range of 500-1000 Å

.

29. A method for fabricating integrated circuits, comprising the steps of:

(a) providing an integrated circuit structure on which transistors have been fabricated;

(b) depositing an interlevel dielectric layer comprising a silicate glass over said transistors;

(c) depositing an insulating etch stop layer over said interlevel dielectric layer;

(d) etching contact holes into said etch stop and interlevel dielectric layers, to expose portions of said transistors for electrical connection;

(e) depositing a layer of metal over said etch stop wherein said metal layer comprises an alloy of aluminum; and

(f) etching said metal layer with a plasma etch chemistry which etches the material of said etch stop layer more slowly than the material of said interlevel dielectric and more slowly than the material of said metal layer, and continuing said etching step for more than 175% of the time required to clear said metal layer from flat surfaces;

whereby said etch stop layer protects said interlevel dielectric from erosion by said metal etching step.

30. The method of claim 29, wherein said metal layer comprises an alloy of aluminum over a barrier layer comprising at least 40% of titanium.