Method of making a vertical integrated circuit
First Claim
1. A method of making a vertical integrated circuit, comprising the steps of:
- a) providing a first substrate comprising a first primary surface provided with at least one first layer having circuit structures and at least one first metallization plane therein;
b) depositing a mask layer on said first primary surface for subsequent use in a dry etching process;
c) forming at least one via hole in said primary surface penetrating said mask layer and said at least one first layer having circuit structures therein;
d) connecting an auxiliary substrate to said first primary surface;
e) reducing the thickness of said first substrate from its surface opposite said first primary surface;
f) providing a second substrate comprising a second primary surface provided with at least one second layer having circuit structures and at least one second metallization plane therein;
g) connecting said first and second substrates by placing said surface opposite said first primary surface and said second primary surface into aligned abutment with each other;
h) removing said auxiliary substrate;
i) deepening said at least one via hole to extend to said second metallization plane; and
j) forming an electrically conductive interconnection between said first and second metallization planes through said via holes.
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Accused Products
Abstract
A method of making a vertical integrated circuit by providing first and second substrates surfaces of which have layers with circuit structures and metallization planes therein, by providing an etching mask on a primary surface of the first substrate, forming via holes in the first substrate extending through the masking surface and the layers of the first substrate, reducing the thickness of the first substrate from a surface opposite its layer surface, alignedly connecting the first substrate by its reduced surface to the layer surface of the second substrate, subsequent deepening of the via holes to the metallization plane of the second substrate and forming electrical interconnection between the metallization planes in the first and second substrates through the via holes.
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Citations
13 Claims
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1. A method of making a vertical integrated circuit, comprising the steps of:
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a) providing a first substrate comprising a first primary surface provided with at least one first layer having circuit structures and at least one first metallization plane therein; b) depositing a mask layer on said first primary surface for subsequent use in a dry etching process; c) forming at least one via hole in said primary surface penetrating said mask layer and said at least one first layer having circuit structures therein; d) connecting an auxiliary substrate to said first primary surface; e) reducing the thickness of said first substrate from its surface opposite said first primary surface; f) providing a second substrate comprising a second primary surface provided with at least one second layer having circuit structures and at least one second metallization plane therein; g) connecting said first and second substrates by placing said surface opposite said first primary surface and said second primary surface into aligned abutment with each other; h) removing said auxiliary substrate; i) deepening said at least one via hole to extend to said second metallization plane; and j) forming an electrically conductive interconnection between said first and second metallization planes through said via holes. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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Specification