Method of making a vertical integrated circuit

• US 5,766,984 A
• Filed: 09/22/1995
• Issued: 06/16/1998
• Est. Priority Date: 09/22/1994
• Status: Expired due to Term

• Current Assignee: Fraunhofer Gesellschaft Zur Foerderung Der Angewandten Forsching E.V.
• Original Assignee: Fraunhofer Gesellschaft Zur Foerderung Der Angewandten Forsching E.V.
• Inventors: Ramm, Peter, Buchner, Reinhold
• Primary Examiner(s): Niebling, John
• Assistant Examiner(s): TURNER, KEVIN F
• Application Number:
  US08/532,367
• Time in Patent Office: 998 Days
• Field of Search: 437/915, 437/924, 437/208
• US Class Current: 438/109
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 438/975 Substrate or mask aligning feature

Abstract

A method of making a vertical integrated circuit by providing first and second substrates surfaces of which have layers with circuit structures and metallization planes therein, by providing an etching mask on a primary surface of the first substrate, forming via holes in the first substrate extending through the masking surface and the layers of the first substrate, reducing the thickness of the first substrate from a surface opposite its layer surface, alignedly connecting the first substrate by its reduced surface to the layer surface of the second substrate, subsequent deepening of the via holes to the metallization plane of the second substrate and forming electrical interconnection between the metallization planes in the first and second substrates through the via holes.

Claims

1. A method of making a vertical integrated circuit, comprising the steps of:

a) providing a first substrate comprising a first primary surface provided with at least one first layer having circuit structures and at least one first metallization plane therein;

b) depositing a mask layer on said first primary surface for subsequent use in a dry etching process;

c) forming at least one via hole in said primary surface penetrating said mask layer and said at least one first layer having circuit structures therein;

d) connecting an auxiliary substrate to said first primary surface;

e) reducing the thickness of said first substrate from its surface opposite said first primary surface;

f) providing a second substrate comprising a second primary surface provided with at least one second layer having circuit structures and at least one second metallization plane therein;

g) connecting said first and second substrates by placing said surface opposite said first primary surface and said second primary surface into aligned abutment with each other;

h) removing said auxiliary substrate;

i) deepening said at least one via hole to extend to said second metallization plane; and

j) forming an electrically conductive interconnection between said first and second metallization planes through said via holes.

2. The method of claim 1, further comprising the steps of:

k) providing first marking indicia in said primary surface and penetrating said at least one layer having first circuit structures, prior to connecting said first substrate with said auxiliary substrate;

1) providing second marking indicia in said second primary surface; and

m) aligning said surface opposite said first substrate and said second primary surface of said second substrate are by means of a visual light optical beam splitter cooperating with said first and second marking indicia.

3. The method of claim 2, wherein said first marking indicia comprise etchings in said first circuit structure layers and wherein said second marker indicia comprise metallic structures in said second metallization plane.

4. The method of claim 3, wherein said step of forming said at least one via hole comprises an etching process.

5. The method of claim 4, wherein said at least one via hole is formed to extend below said first circuit structure layers and wherein said reduction in thickness of said first substrate extends to said at least one via hole.

6. The method of claim 4, wherein said first substrate comprises an SOI substrate having an oxide layer therein and wherein said at least one via hole is formed to extend to said oxide layer and wherein said reduction in thickness extends to said oxide layer.

7. The method of claim 6, wherein said thickness is reduced by an etching process.

8. The method of claim 6, wherein said thickness is reduced by a grinding process.

9. The method of claim 6, further comprising the step of providing a transparent adhesion layer deposited on said second primary surface of said second substrate for connecting said first and second substrates.

10. The method of claim 9, further comprising the step of providing a second adhesion layer for connecting said first substrate with said auxiliary substrate.

11. The method of claim 10, wherein said transparent and said second adhesion layers are passivation layers.

12. The method of claim 11, wherein said transparent and said second adhesion layers are planarizing layers.

13. The method of claim 1, wherein said step of forming an electrically conductive interconnection comprises:

forming at least one contact hole in said first layer opening to said first metallization plane of said first substrate;

insulating the side wall of said at least one via hole; and

covering and connecting said at least one via hole and said at least one contact hole with a metallic material extending between said first and second metallization planes.