Microelectronic encapsulation methods and equipment

• US 5,766,987 A
• Filed: 09/22/1995
• Issued: 06/16/1998
• Est. Priority Date: 09/22/1995
• Status: Expired due to Term

• Current Assignee: Tessera, Inc. (Adeia, Inc.)
• Original Assignee: Tessera, Inc. (Adeia, Inc.)
• Inventors: Mitchell, Craig, Distefano, Thomas H.
• Primary Examiner(s): Niebling, John
• Assistant Examiner(s): LEBENTRITT, MICHAEL
• Application Number:
  US08/532,235
• Time in Patent Office: 998 Days
• Field of Search: 437/182, 437/205, 437/226, 437/209, 257/687, 257/735, 257/747, 257/751, 257/787, 438/126, 438/127
• US Class Current: 438/126
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Microelectronic assemblies such as semiconductor chip assemblies are encapsulated. During encapsulation, the terminals carried by a dielectric layer in each assembly, and the bottom surface of the semiconductor chip in each assembly are protected by covering layers. The covering layers confine the liquid encapsulant and prevent contamination of the terminals and chip bottom surfaces. The encapsulation process may be conducted by using a tilting fixture. The liquid encapsulant and the assemblies are placed into the fixture, the fixture is closed and evacuated, and the encapsulant is then poured onto the assemblies while maintaining the fixture under vacuum. The fixture is then pressurized and maintained under pressure during cure of the encapsulant.

Claims

1. A method of encapsulating a plurality of microelectronic subassemblies comprising the steps of:

providing a plurality of subassemblies each incorporating a dielectric layer overlying a surface of a microelectronic element, terminals on a top surface of the dielectric layer and leads connecting the terminals to contacts on the microelectronic element, said subassemblies being disposed side-by-side so that said microelectronic elements are side-by-side and so that said dielectric layers are disposed side-by-side, said dielectric layers defining openings;

filling a liquid composition between said dielectric layers and microelectronic elements while substantially preventing flow of said liquid onto said top surfaces of said dielectric layers through said openings;

applying a top covering layer extending over said top surfaces of said dielectric layers and occluding said openings so that said top covering layer prevents flow of said liquid onto said top surfaces during said filling step.

2. A method as claimed in claim 1 wherein the dielectric layer of each said subassembly includes some of said openings.

3. A method as claimed in claim 1 wherein said dielectric layers of said plural subassemblies are formed separately from one another so that dielectric layers of adjacent subassemblies define at least some of said openings therebetween, and wherein said top covering layer extends between the dielectric layers of adjacent subassemblies.

4. A method as claimed in claim 3 further comprising the steps of curing said liquid to form a gel or solid and then severing said top covering layer, so that a portion of said top covering layer remains on the dielectric layer of each said subassembly.

5. A method as claimed in claim 4 further comprising the step of providing holes in said top covering layer so that said holes are disposed in registry with the terminals of each said subassembly.

6. A method as claimed in claim 5 wherein said holes are formed before the top covering layer is applied to said dielectric layers.

7. A method as claimed in claim 5 wherein said holes are formed after said curing step.

8. A method as claimed in claim 1 further comprising the steps of curing said liquid to form a gel or solid and then removing said top covering layer.

9. A method as claimed in claim 8 wherein said step of providing said top covering layer includes the step of releasably bonding said top covering layer to said top surfaces of said dielectric layers.

10. A method as claimed in claim 9 wherein said step of removing said top covering layer includes the step of peeling said top covering layer away from said dielectric layers.

11. A method as claimed in claim 8 wherein said step of removing said top covering layer includes the step of dissolving said top covering layer.

12. A method as claimed in claim 1 wherein said step of providing said top covering layer includes the step of providing a solid layer and a layer of a soft sealant so that said sealant is disposed between said solid layer and said dielectric layers of said subassemblies, and so that said sealant substantially encapsulates said terminals.

13. A method as claimed in claim 12 further comprising the step of removing said solid layer and said sealant.

14. A method as claimed in claim 12 wherein said sealant adheres to said solid layer and to said dielectric layers of said subassembly, whereby said sealant secures said solid layer to said dielectric layers.

15. A method as claimed in claim 1 wherein the subassemblies are disposed between a bottom fixture element and a top fixture element so that the top surfaces of the dielectric layers face toward the top fixture and bottom surfaces of the microelectronic elements face toward the bottom fixture during said filling step, said top covering layer being disposed between said dielectric layers and said top fixture during said filling step.

16. A method of encapsulating a plurality of microelectronic subassemblies comprising the steps of:

providing a plurality of subassemblies each incorporating a dielectric layer overlying a surface of a microelectronic element, terminals on a top surface of the dielectric layer and leads connecting the terminals to contacts on the microelectronic element, said subassemblies being disposed side-by-side so that said microelectronic elements are side-by-side and so that said dielectric layers are disposed side-by-side, said microelectronic elements being separate from one another and defining openings therebetween, said microelectronic elements having bottom surfaces facing away from the dielectric layers;

filling a liquid between said dielectric layers and microelectronic elements while substantially preventing flow of said liquid onto said bottom surfaces of said microelectronic elements through said openings;

providing a bottom covering layer overlying the bottom surfaces of the microelectronic elements and occluding said openings, whereby said bottom covering layer will prevent said flow.

17. A method as claimed in claim 16 further comprising the steps of curing said liquid to a gel or solid and then removing said bottom covering layer.

18. A method as claimed in claim 16 wherein the subassemblies are disposed side-by-side between a bottom fixture element and a top fixture element so that the top surfaces of the dielectric layers face toward the top fixture and bottom surfaces of the microelectronic elements face toward the bottom fixture during said filling step, said bottom covering layer being disposed between said microelectronic elements and said bottom fixture during said filling step.

20. A method as claimed in claim 18 wherein said step of placing the microelectronic device includes the step of placing a plurality of microelectronic subassemblies, each including a microelectronic element, a dielectric layer with terminals thereon and leads connecting the terminals to the microelectronic element into said device-receiving pocket.

21. A method as claimed in claim 20 wherein said fixture includes a bottom element defining a support surface, said placing step including the step of placing said subassemblies side-by-side on said support surface.

22. A method as claimed in claim 21 wherein said subassemblies are connected to one another to form a panel, said placing step including the step of depositing said panel onto said support surface of said bottom element.

23. A method as claimed in claim 22 wherein said fixture further includes a top element, the method further including the step of assembling said top element to said bottom element after said depositing step so that said panel is disposed between said top element and said bottom element.

24. A method as claimed in claim 21 wherein said panel includes a top covering layer overlying said dielectric layers of said subassemblies, and extending beyond said subassemblies, said step of sealing said fixture including the step of sealing said top covering layer to said bottom element of said fixture.

19. A method of encapsulating a microelectronic device comprising the steps of:

(a) placing the microelectronic device in a device-receiving pocket of a fixture;

(b) placing a liquid encapsulant in a well in said fixture while said fixture is in a first orientation in which said well extends downwardly and said liquid is confined by gravity in said well;

(c) sealing said fixture and evacuating air from within said fixture, to thereby degas said encapsulant and remove air from around said microelectronic device;

(d) while said fixture remains sealed, turning the fixture to a second orientation to thereby pour the liquid encapsulant into the device-receiving pocket so that the liquid encapsulant surrounds the microelectronic device; and

(e) curing the liquid encapsulant to a solid or gel surrounding the microelectronic device.

25. A method as claimed in claim 19 further comprising the step of injecting a gas under pressure above said encapsulant after said turning step.

26. A method as claimed in claim 25 wherein said gas is maintained under pressure during said curing step.