Method for making self-aligned bipolar transistor
First Claim
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1. A method for manufacturing a semiconductor device comprising the steps of:
- forming a collector layer of a first conductivity type on a semiconductor substrate;
forming an insulating layer having an opening for exposing said collector layer on said semiconductor substrate;
forming a base electrode including an end, wherein the end projects to said opening on said insulating layer;
growing a first semiconductor layer of a second conductive type on said collector layer and a second semiconductor layer of the second conductive type between said first semiconductor layer and said end of said base electrode, thereby electrically connecting said first semiconductor layer and said second semiconductor layer in said opening;
selectively removing said first semiconductor layer to expose said collector layer, thereby a remaining portion of said first semiconductor layer serving as an outer base layer;
forming an inner base layer of said second conductivity type to cover said collector layer and said outer base layer and said second semiconductor layer; and
forming an emitter layer of said first conductivity type on said inner base layer.
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Abstract
A SiGe alloy film containing electrically active impurity in a concentration higher than the intrinsic base layer is formed on the eaves-structured polycrystalline silicon film for base electrode. After that, SiGe only just under the opening is removed completely by dry etching under a condition that etching speed of SiGe is faster than that of Si, and subsequently the intrinsic base layer is formed.
69 Citations
10 Claims
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1. A method for manufacturing a semiconductor device comprising the steps of:
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forming a collector layer of a first conductivity type on a semiconductor substrate; forming an insulating layer having an opening for exposing said collector layer on said semiconductor substrate; forming a base electrode including an end, wherein the end projects to said opening on said insulating layer; growing a first semiconductor layer of a second conductive type on said collector layer and a second semiconductor layer of the second conductive type between said first semiconductor layer and said end of said base electrode, thereby electrically connecting said first semiconductor layer and said second semiconductor layer in said opening; selectively removing said first semiconductor layer to expose said collector layer, thereby a remaining portion of said first semiconductor layer serving as an outer base layer; forming an inner base layer of said second conductivity type to cover said collector layer and said outer base layer and said second semiconductor layer; and forming an emitter layer of said first conductivity type on said inner base layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Current AssigneeNEC Electronics Corporation (Renesas Electronics Corporation)
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Original AssigneeNEC Corporation
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InventorsSato, Fumihiko
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Primary Examiner(s)Niebling, John
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Assistant Examiner(s)Pham, Long
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Application NumberUS08/623,573Time in Patent Office810 DaysField of Search148/DIG. 10, 148/11, 257/197, 257/198, 257/591, 257/592, 257/593, 438/309, 438/341, 438/933US Class Current438/309CPC Class CodesH01L 29/66242 Heterojunction transistors ...Y10S 438/933 Germanium or silicon or Ge-...
