Method for forming a low impurity diffusion polysilicon layer

• US 5,767,004 A
• Filed: 04/22/1996
• Issued: 06/16/1998
• Est. Priority Date: 04/22/1996
• Status: Expired due to Fees

• Current Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Inventors: Jang, Chuck, Kong, Ching Win, Balasubramanian, Narayanan
• Primary Examiner(s): Bowers, Jr., Charles L.
• Assistant Examiner(s): Thomas, Toniae M.
• Application Number:
  US08/635,992
• Time in Patent Office: 785 Days
• Field of Search: 437/40 GS, 437/41 GS, 437/247, 437/101, 438/592, 438/301, 438/197
• US Class Current: 438/592
• CPC Class Codes: H01L 21/28061 the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction H01L21/28052 takes precedence
• CPC Class Codes: H01L 21/32055 Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
• CPC Class Codes: H01L 29/4925 with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with only a vertical doping structure or vertical doping variation H01L29/4916
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941

Abstract

A method for forming within an integrated circuit a low impurity diffusion polysilicon layer. Formed upon a semiconductor substrate is an amorphous silicon layer. Formed also upon the semiconductor substrate and contacting the amorphous silicon layer is a polysilicon layer. The amorphous silicon layer and the polysilicon layer are then simultaneously annealed to form a low impurity diffusion polysilicon layer. The low impurity diffusion polysilicon layer is a polysilicon multi-layer with grain boundary mis-matched polycrystalline properties. Optionally, a metal silicide layer may be formed upon the amorphous silicon layer and the polysilicon layer either prior to or subsequent to annealing the amorphous silicon layer and the polysilicon layer. The metal silicide layer and low impurity diffusion polysilicon layer may then be patterned to form a polycide gate electrode.

Claims

1. A method for forming an impurity diffusion inhibited polysilicon layer comprising:

forming over a semiconductor substrate an amorphous silicon layer;

forming over the semiconductor substrate a polysilicon layer in contact with the amorphous silicon layer;

annealing simultaneously the amorphous silicon layer and the polysilicon layer to form an impurity diffusion inhibited polysilicon layer, the impurity diffusion inhibited polysilicon layer being a polysilicon multi-layer with grain boundary mis-matched polycrystalline properties; and

forming adjoining the impurity diffusion inhibited polysilicon layer a metal silicide layer, the impurity diffusion inhibited polysilicon layer inhibiting diffusion of impurities from within the impurity diffusion inhibited polysilicon layer and the impurity diffusion inhibited polysilicon layer inhibiting diffusion of impurities through the impurity diffusion inhibited polysilicon layer from the metal silicide layer.

2. The method of claim 1 wherein the amorphous silicon layer is from about 400 to about 700 angstroms thick.

3. The method of claim 1 wherein the amorphous silicon layer is formed through a Low Pressure Chemical Vapor Deposition (LPCVD) method employing silicone as a silicon source material.

4. The method of claim 3 wherein the Low Pressure Chemical Vapor Deposition (LPVCD) method is undertaken at a deposition temperature of from about 500 to about 580 degrees centigrade.

5. The method of claim 1 wherein the polysilicon layer is from about 1000 to about 1500 angstroms thick.

6. The method of claim 1 wherein the polysilicon layer is formed through a Low Pressure Chemical Vapor Deposition (LPCVD) method employing silicone as a silicon source material.

7. The method of claim 6 wherein the Low Pressure Chemical Vapor Deposition (LPCVD) method is undertaken at a deposition temperature of from about 600 to about 700 degrees centigrade.

8. The method of claim 1 wherein the amorphous silicon layer and the polysilicon layer are simultaneously thermally annealed through a conventional thermal method at a temperature of from about 800 to about 950 degrees centigrade for a time period of from about 15 to about 45 minutes.

9. The method of claim 1 wherein the amorphous silicon layer is formed over the semiconductor substrate prior to forming the polysilicon layer over the semiconductor substrate.

10. The method of claim 1 wherein the polysilicon layer is formed over the semiconductor substrate prior to forming the amorphous silicon layer over the semiconductor substrate.

22. The method of claim 1 wherein the metal silicide layer the is a tungsten silicide layer formed through a Chemical Vapor Deposition (CVD) method employing tungsten hexafluoride as a tungsten source material.

11. A method for forming an impurity diffusion inhibited polycide gate electrode for use within a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) comprising:

forming over a semiconductor substrate an amorphous silicon layer;

forming over the semiconductor substrate a polysilicon layer contacting the amorphous silicon layer;

annealing simultaneously the amorphous silicon layer and the polysilicon layer to form an impurity diffusion inhibited polysilicon layer, the impurity diffusion inhibited polysilicon layer being a polysilicon multi-layer having grain boundary mis-matched polycrystalline properties;

forming contacting the impurity diffusion inhibited polysilicon layer a metal silicide layer, the impurity diffusion inhibited polysilicon layer inhibiting diffusion of impurities from within the impurity diffusion inhibited polysilicon layer and the impurity diffusion inhibited polysilicon layer inhibiting diffusion of impurities through the impurity diffusion inhibited polysilicon layer from the metal silicide layer; and

patterning the metal silicide layer and the impurity diffusion inhibited polysilicon layer to form a polycide gate electrode.

12. The method of claim 11 wherein the amorphous silicon layer is from about 400 to about 700 angstroms thick.

13. The method of claim 11 wherein the amorphous silicon layer is formed through a Low Pressure Chemical Vapor Deposition (LPCVD) method employing silicone as a silane source material.

14. The method of claim 13 wherein the Low Pressure Chemical Vapor Deposition (LPCVD) method is undertaken at a deposition temperature of from about 500 to about 580 degrees centigrade.

15. The method of claim 11 wherein the polysilicon layer is from about 1000 to about 1500 angstroms thick.

16. The method of claim 11 wherein the polysilicon layer is formed through a Low Pressure Chemical Vapor Deposition (LPCVD) method employing silicone as a silane source material.

17. The method of claim 16 wherein the Low Pressure Chemical Vapor Deposition (LPCVD) method is undertaken at a deposition temperature of from about 600 to about 700 degrees centigrade.

18. The method of claim 11 wherein the amorphous silicon layer and the polysilicon layer are thermally annealed through a conventional thermal method at a temperature of from about 800 to about 950 degrees centigrade for a time period of from about 15 to about 45 minutes.

19. The method of claim 11 wherein the amorphous silicon layer is formed over the semiconductor substrate prior to forming the polysilicon layer over the semiconductor substrate.

20. The method of claim 11 wherein the metal silicide layer is a tungsten silicide layer.

21. The method of claim 20 wherein the tungsten silicide is formed through a Chemical Vapor Deposition (CVD) method employing tungsten hexafluoride as a tungsten source material.