Method of etching a polysilicon pattern

• US 5,767,018 A
• Filed: 11/08/1995
• Issued: 06/16/1998
• Est. Priority Date: 11/08/1995
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Bell, Scott A.
• Primary Examiner(s): Breneman, R. Bruce
• Assistant Examiner(s): ALANKO, ANITA KAREN
• Application Number:
  US08/554,412
• Time in Patent Office: 951 Days
• Field of Search: 437/228, 156/650.1, 156/651.1, 156/652.1, 156/653.1, 156/646.1, 156/657.1, 438/696, 438/720, 438/733, 438/738, 438/742, 438/743, 438/744, 438/906, 438/911, 438/963, 216/46
• US Class Current: 438/696
• CPC Class Codes: H01L 21/32135 by vapour etching only
• CPC Class Codes: H01L 21/32139 using masks

Abstract

Pitting in active regions along the edges of a gate electrode when etching a composite comprising an anti-reflective coating on polysilicon is avoided by etching the anti-reflective coating with an etchant that forms a protective passivating coating on at least the sidewalls of the etched anti-reflective pattern and on the underlying polysilicon layer. Subsequently, anisotropic etching is conducted to remove the protective passivating coating from the surface of the polysilicon layer, leaving the etched anti-reflective pattern protected from the main polysilicon etch on at least its sidewalls by the passivating coating to prevent interaction. In another embodiment, the anti-reflective coating is etched without formation of a passivating coating, and the polysilicon layer subsequently etched with an etchant that forms a passivating coating.

Claims

1. A method of etching a composite comprising a dielectric underlayer, a polysilicon layer on the dielectric underlayer, and a dielectric coating on the polysilicon layer, which method comprises:

removing portions of the dielectric coating with a first etchant to form a dielectric pattern comprising sidewalls on the polysilicon layer, whereby a passivating coating is formed on at least a sidewall of the dielectric pattern and on the polysilicon layer;

anisotropically etching the passivating coating with a second etchant to expose a portion of the polysilicon layer leaving a portion of the passivating coating on at least the sidewall of the dielectric pattern; and

etching the polysilicon layer with a third etchant to form a polysilicon pattern.

2. The method according to claim 1, further comprising overetching with a fourth etchant to remove a portion of the dielectric underlayer.

3. The method according to claim 1, wherein the dielectric coating comprises a material selected from the group consisting of a silicon oxide, silicon nitride, silicon oxynitride, titanium nitride and titanium oxynitride.

4. The method according to claim 1, wherein the first etchant comprises oxygen.

5. The method according to claim 4, wherein the first etchant further comprises a fluorinated hydrocarbon.

6. The method according to claim 5, wherein the fluorinated hydrocarbon is CHF₃.

7. The method according to claim 1, wherein the second etchant comprises SF₆, Cl₂, He and O₂.

8. The method according to claim 1, wherein the third etchant comprises HBr and Cl₂.

9. The method according to claim 2, wherein the fourth etchant comprises HBr, He and O₂.

10. The method according to claim 1, wherein the etched dielectric pattern is encapsulated with the passivating coating, and the dielectric pattern remains encapsulated with the passivating coating after anisotropic etching.

11. The method according to claim 1, wherein the passivating coating comprises an inorganic or organic material.

12. The method according to claim 11, wherein the passivating coating comprises an organic polymer.

13. The method according to claim 1, wherein the dielectric coating is etched in a first chamber and the subsequent etching steps are conducted in a different second chamber.

14. The method according to claim 1, wherein the passivating coating has a thickness of about 50 to about 1000 Å

.

15. The method according to claim 14, wherein the passivating coating has a thickness of about 100 to about 300 Å

.

16. The method according to claim 1, comprising:

forming a dielectric underlayer;

depositing a polysilicon layer on the dielectric underlayer;

depositing a dielectric coating on the polysilicon layer;

forming a resist mask pattern on the dielectric coating;

removing portions of the dielectric coating with a first etchant to form a dielectric pattern comprising sidewalls on the polysilicon layer, whereby a passivating organic polymeric coating is formed encapsulating the dielectric pattern and on the polysilicon layer;

anisotropically etching the passivating coating with a second etchant to expose a portion of the polysilicon layer, leaving the dielectric pattern encapsulated with the passivating coating;

etching the polysilicon layer with a third etchant to form a pattern; and

overetching with a fourth etchant to remove a portion of the dielectric layer.

17. The method according to claim 16, further comprising depositing the dielectric underlayer on a semiconductor substrate;

depositing a dielectric anti-reflective material on the polysilicon layer; and

etching the polysilicon layer to form a gate electrode of a transistor.

18. The method according to claim 16, wherein the first etchant comprises oxygen and a fluorinated hydrocarbon.

19. The method according to claim 18, wherein the fluorinated hydrocarbon is CHF₃.

20. The method according to claim 16, wherein the second etchant comprises SF₆, Cl₂, He and O₂.

32. The method according to claim 1, comprising etching the polysilicon layer using the etched dielectric coating as a hard mask.

21. A method of manufacturing a semiconductor device, which method comprises:

depositing a dielectric underlayer;

depositing a layer of polysilicon on the dielectric underlayer;

forming a dielectric coating on the polysilicon layer;

removing a portion of the dielectric coating with a first etchant to form a dielectric pattern comprising sidewalls on the polysilicon layer, whereby a passivating polymer-containing coating is formed on at least a sidewall of the dielectric pattern and on the polysilicon layer;

anisotropically etching the passivating coating with a second etchant to expose a portion of the polysilicon layer leaving a portion of the passivating coating on at least the sidewall of the dielectric pattern; and

etching the polysilicon layer with a third etchant to form a pattern.

22. The method according to claim 21, further comprising overetching to remove a portion of the dielectric underlayer with a fourth etchant.

23. The method according to claim 21, further comprising:

depositing the dielectric underlayer on a semiconductor substrate;

depositing a dielectric coating comprising an anti-reflective material selected from the group consisting of a silicon oxide, silicon nitride, silicon oxynitride, titanium nitride, and titanium oxynitride on the polysilicon layer;

forming a resist mask pattern on the dielectric anti-reflective coating; and

etching the polysilicon layer to form a gate electrode of a transistor.

24. The method according to claim 21, wherein the first etchant comprises a fluorinated hydrocarbon and oxygen.

25. The method according to claim 24, wherein the fluorinated hydrocarbon is CHF₃.

26. The method according to claim 21, wherein the second etchant comprises SF₆, Cl₂, He and O₂.

27. The method according to claim 21, wherein the passivating coating encapsulates the dielectric pattern, and the dielectric pattern remains encapsulated with the passivating coating after anisotropic etching.

28. The method according to claim 21, wherein the dielectric coating is etched in a first chamber and the subsequent etching steps are conducted in a different second chamber.

29. The method according to claim 21, wherein the passivating coating has a thickness of about 50 to about 1000 Å

.

30. The method according to claim 29, wherein the passivating coating has a thickness of about 100 to about 300 Å

.

31. The method according to claim 23, wherein the anti-reflective material is a silicon oxynitride.

33. The method according to claim 21, comprising etching the polysilicon layer using the etched dielectric coating as a hard mask.

34. A method of etching a composite comprising a dielectric underlayer, a polysilicon layer on the dielectric underlayer, and a dielectric coating on the polysilicon layer, which method comprises:

removing portions of the dielectric coating with a first etchant to form a dielectric pattern comprising sidewalls on the polysilicon layer, whereby a passivating coating is not formed on the dielectric pattern or the polysilicon layer; and

etching the polysilicon layer with a second etchant to form a polysilicon pattern, whereby a passivating coating is formed on the sidewalls of the etched dielectric pattern while the polysilicon layer is etched.

35. The method according to claim 34, further comprising overetching with a third etchant to remove a portion of the dielectric underlayer.

36. The method according to claim 34, wherein the dielectric coating comprises a material selected from the group consisting of a silicon oxide, silicon nitride, silicon oxynitride, titanium nitride and titanium oxynitride.

37. The method according to claim 34, wherein the first etchant comprises SF₆.

38. The method according to claim 37, wherein the first etchant further comprises Cl₂, He and O₂.

39. The method according to claim 34, wherein the second etchant comprises He and O₂.

40. The method according to claim 39, wherein the second etchant further comprises HBr and Cl₂.

41. The method according to claim 34, wherein the passivating coating comprises an inorganic or organic material.

42. The method according to claim 41, wherein the passivating coating comprises an organic polymer.

43. The method according to claim 42, wherein the passivating coating has a thickness of about 50 to about 1000 Å

.

44. The method according to claim 43, wherein the passivating coating has a thickness of about 100 to about 300 Å

.

45. The method according to claim 34, further comprising:

depositing the dielectric underlayer on a semiconductor substrate;

depositing a dielectric anti-reflective coating on the polysilicon layer; and

etching the polysilicon layer to form a gate electrode of a transistor.

46. The method according to claim 34, comprising etching the polysilicon layer using the etched dielectric coating as a hard mask.

47. The method according to claim 34, comprising etching the dielectric coating and polysilicon layer in the same chamber.