High voltage thin film transistor having a linear doping profile

• US 5,767,547 A
• Filed: 05/23/1995
• Issued: 06/16/1998
• Est. Priority Date: 02/01/1991
• Status: Expired due to Term

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Merchant, Steven L., Arnold, Emil
• Primary Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US08/448,268
• Time in Patent Office: 1,120 Days
• Field of Search: 257/347, 257/350, 257/351, 257/352, 257/353, 257/500, 257/501, 257/502, 257/339, 257/408, 257/409
• US Class Current: 257/347
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/7394 on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/78612 for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
• CPC Class Codes: H01L 29/78624 the source and the drain regions being asymmetrical
• CPC Class Codes: H01L 29/861 Diodes

Abstract

The present invention is directed to a thin film transistor having a linear doping profile between the gate and drain regions. This is constructed in a particular manner in order to achieve a thin film transistor having a significantly high breakdown voltage of the order of 700 to 900 volts, much greater than that achieved in the prior art.

Claims

1. A high voltage, semiconductor-on-insulator electronic device, comprising:

a substrate;

a first insulating layer disposed on the substrate, the first insulating layer having a first insulating layer thickness;

a semiconductor layer disposed on the first insulating layer, wherein the semiconductor layer further comprises in lateral sequence a source region, a body region, a thin drift region and a drain region;

a gate oxide layer disposed atop the source, body and drift regions;

a gate region disposed atop the gate oxide layer;

a second insulating layer next to the gate oxide layer and the gate region and disposed atop the drift region;

wherein the drift region has a length L, describing the distance between the body region and the drain region along the drift region, a drift region thickness perpendicular to said length L, and a substantially linear doping profile along the length L of said drift region, from a minimum value the drift region adjacent to the body region, to a maximum value adjacent to the drain region;

wherein length L is substantially in the range of 10 microns to 60 microns;

wherein the drift region thickness is less than or equal to about 1 micron;

wherein the substantially linear doping profile is described at any point along the length of the drift region X microns distant from the body region by the relationship;

space="preserve" listing-type="equation">Q(X)=Q(0)+(X/L)Q.sub.max

where Q(0) is the minimum number of dopant ions per unit area in the drift region adjacent to the body region, and is substantially in the range of 1×

10₁₁ /cm² to about 1×

10¹² /cm² ;

Q^max is substantially in the range of 5×

10¹² /cm² to about 2×

10¹³ /cm², and Q(0)+Q_max is the maximum number of dopant ions per unit area adjacent to the drain region; and

wherein the combination of the drift region having a thickness less than or equal to 1 micron and the substantially linear doping profile provides a higher breakdown voltage for the device.

2. The device of claim 1, wherein the first insulating layer thickness is substantially in the range of about 2 to 6 microns.

3. The device of claim 1, wherein the drift region thickness is substantially in the range of about 0.1 to 0.3 microns.

4. The device of claim 1, wherein the drift region thickness is in the range of about 0.1-0.3 microns, the length of the drift region is about 50 microns, and the first insulating layer thickness is approximately 2 microns.

5. The device of claim 1, wherein the substrate comprises silicon, the first and second insulating layers comprise silicon dioxide and the semiconductor layer comprises silicon.

6. The device of claim 5, wherein the semiconductor layer comprises monocrystalline silicon.

7. The device of claim 5, wherein the substrate is either n or p type silicon.

8. The device of claim 1, wherein the gate region comprises a polysilicon gate.