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Structure for ESD protection in semiconductor chips

  • US 5,767,552 A
  • Filed: 06/05/1997
  • Issued: 06/16/1998
  • Est. Priority Date: 11/30/1995
  • Status: Expired due to Term
First Claim
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1. An ESD protected CMOS semiconductor structure, comprising:

  • a lateral CMOS transistor having a source and a drain comprising first and second n+ doped active areas;

    a first n-well resistor formed at least partially under the first active transistor area and conductively coupled thereto;

    a third n+ area formed adjacently spaced from the first active transistor area and conductively coupled to the first n-well resistor;

    a first and a second independent conductive layer formed on top of the first and third areas respectively, and insulated therefrom by an insulating layer, said conductive layers having independent sets of electrical contacts formed to contact the first and third areas respectively such that the electrical resistance observed between the sets of contacts comprises resistance provided by the first n-well resistor;

    a second n-well resistor formed at least partially under the second active transistor area and conductively coupled thereto;

    a fourth n+ area formed adjacently spaced from the second active transistor area and conductively coupled to the second n-well resistor;

    a third and a fourth independent conductive layer formed on top of the second and fourth areas respectively and insulated therefrom by an insulating layer, said conductive layers having independent sets of electrical contacts formed to contact the second and fourth areas respectively such that the electrical resistance observed between the sets of contacts comprises resistance provided by the second n-well resistor.

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