Surface mount and flip chip technology with diamond film passivation for total integated circuit isolation

• US 5,767,578 A
• Filed: 04/19/1996
• Issued: 06/16/1998
• Est. Priority Date: 10/12/1994
• Status: Expired due to Term

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Fusser, Hans-Jurgen, Hshieh, Fwu-Iuan, Ho, Yueh-Se, Owyang, King, Chang, Mike F., Dun, Jowei, Zachai, Reinhard
• Primary Examiner(s): CARROLL, JAMES J
• Application Number:
  US08/634,957
• Time in Patent Office: 788 Days
• Field of Search: 257/684, 257/705-7, 257/77, 257/501, 257/502, 257/510, 257/513, 257/675, 257/712-3, 257/717
• US Class Current: 257/717
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/29 characterised by the material , e.g. carbon interlayer dielectrics H01L23/5329
• CPC Class Codes: H01L 23/3672 Foil-like cooling fins or heat sinks being part of lead-frames H01L23/49568
• CPC Class Codes: H01L 23/3732 Diamonds
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/14 Integrated circuits

Abstract

An integrated circuit chip has full trench dielectric isolation of each portion of the chip. Initially the chip substrate is of conventional thickness and has semiconductor devices formed in it. After etching trenches in the substrate and filling them with dielectric material, a heat sink cap is attached to the passivation layer on the substrate front side surface. The passivation layer is a CVD diamond film which provides both electrical insulation and thermal conductivity. The substrate backside surface is removed (by grinding and/or CMP) to expose the bottom portion of the trenches. This fully isolates each portion of the die and eliminates mechanical stresses at the trench bottoms. Thereafter drain or collector electrical contacts are provided on the substrate backside surface. In a flip chip version, frontside electrical contacts extend through the frontside passivation layer to the heat sink cap. In a surface mount version, vias are etched through the substrate, with surface mount posts formed on the vias, to contact the frontside electrical contacts and provide all electrical contacts on the substrate backside surface. The wafer is then scribed into die in both versions without need for further packaging.

Claims

1. An integrated circuit comprising:

a semiconductor substrate having a principal surface;

a plurality of semiconductor devices formed in the substrate;

a pattern of conductive lines formed overlying the principal surface and in electrical contact with the devices;

an electrically insulating film at least partially overlying the pattern of conductive lines;

a thermally conductive plate bonded to the insulating film and overlying the pattern of conductive lines and overlying the plurality of semiconductor devices, the plate being insulated from the pattern of conductive lines by the insulating film, wherein the plate provides mechanical support for the substrate and the pattern of conductive lines, and whereby the plate is a part of the completed integrated circuit;

a plurality of insulated trenches extending from the principal surface of the substrate through the substrate and to an opposing backside surface thereof;

a plurality of through holes defined in the plate; and

a plurality of electrical contacts, one electrical contact extending through each of the through holes and being in electrical contact with one of the semiconductor devices.

2. A method of forming an integrated circuit, comprising the steps of:

providing a semiconductor substrate having a principal surface;

forming a plurality of semiconductor devices in the substrate;

forming a plurality of trenches in the substrate extending from the principal surface thereof into the substrate to a particular depth;

forming a layer of insulating material in each of the trenches;

forming a first pattern of conductive lines overlying the principal surface and in electrical contact with the devices;

forming an electrically insulating film layer overlying the substrate;

permanently bonding a thermal conductive plate to the insulating film layer and overlying the principal surface of the substrate;

removing a portion of the substrate from a backside surface thereof opposing the principal surface, thereby exposing at least a bottom part of each of the trenches;

forming a second pattern of conductive lines on a surface of the plate prior to the step of bonding; and

electrically contacting portions of the second pattern to portions of the first pattern.

3. An integrated circuit comprising:

a semiconductor substrate having a principal surface;

a plurality of semiconductor devices formed in the substrate;

a pattern of conductive lines formed overlying the principal surface and in electrical contact with the devices;

an electrically insulating film at least partially overlying the pattern of conductive lines;

a thermally conductive plate bonded to the insulating film and overlying the pattern of conductive lines and overlying the plurality of semiconductor devices, the plate being insulated from the pattern of conductive lines by the insulating film, wherein the plate provides mechanical support for the substrate and the pattern of conductive lines, and whereby the plate is a part of the completed integrated circuit;

a plurality of trenches each filled with dielectric material and extending from the principal surface of the substrate through the substrate and to an opposing backside surface thereof, wherein the trenches dielectrically isolate the semiconductor devices from one another;

a plurality of through holes defined in the plate; and

a plurality of electrical contacts, one electrical contact extending through each of the through holes and being in electrical contact with one of the semiconductor devices.

4. The integrated circuit of claim 3, further comprising a plurality of electrically conductive contacts formed on the backside surface of the substrate, each conductive contact being in contact with a selected portion of the backside surface as defined by the plurality of trenches.

5. The integrated circuit of claim 3, wherein a thickness of the substrate is less than about 100 micrometers.

6. The integrated circuit of claim 3, further comprising a second pattern of conductive lines juxtaposed to the plate and in electrical contact with the first pattern.

7. The integrated circuit of claim 3, wherein the substrate defines a plurality of conductive vias extending from the principal surface thereof to the backside surface thereof, each via being in electrical contact on the principal surface with a portion of the pattern of conductive lines, and each via forming an electrical contact on the backside surface.

8. The integrated circuit of claim 7, wherein the electrical contacts on the backside surface are each a post extending from the backside surface.

9. The integrated circuit of claim 3, wherein the insulating film has a thickness in the range of 0.5 to 10 micrometers.

10. The integrated circuit of claim 3, wherein the insulating film is bonded to the plate by a thermally conductive adhesive layer.

11. The integrated circuit of claim 3, wherein the insulating film is a diamond film.

12. A method of forming an integrated circuit, comprising the steps of:

providing a semiconductor substrate having a principal surface;

forming a plurality of semiconductor devices in the substrate;

forming a plurality of trenches in the substrate extending from the principal surface thereof into the substrate to a particular depth;

filling each of the trenches with dielectric material wherein the trenches dielectrically isolate the semiconductor devices from one another;

forming a pattern of conductive lines overlying the principal surface and in electrical contact with the devices;

forming an electrically insulating film layer overlying the substrate;

bonding a thermal conductive plate to the insulating film layer and overlying the principal surface of the substrate and overlying the plurality of semiconductor devices, the plate being insulated from the pattern of conductive lines by the insulating film layer, wherein the plate provides mechanical support for the substrate and the pattern of conductive lines, and whereby the plate is part of the completed integrated circuit;

removing a portion of the substrate from a backside surface thereof opposing the principal surface, thereby exposing at least a bottom part of each of the trenches and reducing a thickness of the substrate;

forming a second pattern of conductive lines on a surface of the plate prior to the step of bonding; and

electrically contacting portions of the second pattern to portions of the first pattern.

13. The method of claim 12, further comprising the steps of:

forming a conductive layer on the backside surface; and

patterning the conductive layer into a plurality of contact regions, each contact region being in contact with a selected portion of the backside surface as defined by the plurality of trenches.

14. The method of claim 12 wherein the step of removing leaves a remaining thickness of the substrate of less than about 100 micrometers.

15. The method of claim 12 wherein the step of bonding comprises applying a thermally conductive adhesive between the insulating film layer and the plate.

16. The method of claim 12, further comprising the steps of:

forming a plurality of vias extending from the backside surface to the principal surface of the substrate, after the step of removing;

providing conductive material in each of the vias, the conductive material in each via being in electrical contact on the principal surface with a portion of the pattern of conductive lines, and the conductive material in each via forming an electrical contact on the backside surface.

17. The method of claim 16, wherein the step of providing conductive material comprises forming a layer of the conductive material on the backside surface, and further comprising:

forming the layer of conductive material into a plurality of posts extending outward from the backside surface, each post being electrically connected to the conductive material in one of the vias.

18. The method of claim 12, wherein the insulating film layer is formed to a thickness in a range of 0.5 to 10 micrometers.

19. The method of claim 12, wherein the insulating film is a diamond film.