Four terminal RF mixer device

• US 5,767,726 A
• Filed: 10/21/1996
• Issued: 06/16/1998
• Est. Priority Date: 10/21/1996
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Wang, Hongmo
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): Wells, Kenneth B.
• Application Number:
  US08/734,658
• Time in Patent Office: 603 Days
• Field of Search: 327/113-122, 327/355, 327/356, 331/42, 331/333, 333/25, 333/218, 455/318, 455/319, 455/326, 455/330, 455/333
• US Class Current: 327/356
• CPC Class Codes: H03D 2200/0043 Bias and operating point
• CPC Class Codes: H03D 2200/0084 Lowering the supply voltage and saving power
• CPC Class Codes: H03D 7/125 with field effect transistors
• CPC Class Codes: H03D 7/1441 using field-effect transistors H03D7/145 takes precedence
• CPC Class Codes: H03D 7/1458 Double balanced arrangements, i.e. where both input signals are differential

Abstract

A four terminal multiplication circuit capable of mixing up to three input signals. The circuit includes a MOS transistor having gate, source, drain and back-gate terminals. When the circuit is used as an RF mixer or downconverter, an RF signal is provided to the gate terminal and a local oscillator signal is provided to the back-gate terminal. A DC voltage is applied to the source terminal for biasing the transistor and the mixed/downconverted output (IF) signal is obtained from the drain terminal. A single balanced and a double balanced mixer circuit are also disclosed. In the single balanced circuit, two MOS transistors are used; the RF signal is applied to the gate terminals with the positive phase LO component applied to one back-gate terminal and the negative phase local oscillator (LO) component applied to the other back-gate terminal for producing a positive phase and a negative phase IF signal. In the double balanced circuit, four MOS transistors are used; the positive phase RF signal is applied to the gate terminals of two of the transistors and the negative phase RF signal is applied to the gate terminals of the other two transistors. Likewise, the positive phase LO signal is applied to two of the transistors and the negative phase LO signal is applied to the other two transistors.

Claims

1. A method of mixing a plurality of frequency dependent input signals to form a frequency dependent output signal using a MOS transistor having a gate terminal, a source terminal, a back-gate terminal and a drain terminal, said method comprising the steps of:

providing a first input signal having frequency components to the gate terminal;

providing a second input signal having frequency components to the back-gate terminal;

providing a third input signal to the source terminal; and

obtaining from the drain terminal an output signal which is a function of at least the first and second input signals.

2. The method of claim 1, wherein the third input signal comprises a DC voltage.

3. The method of claim 1, wherein the third input signal comprises a frequency dependent signal.

4. The method of claim 1, wherein the first frequency dependent input signal comprises a received RF signal having a predetermined first center frequency and wherein the second frequency dependent signal comprises a local oscillator signal having a predetermined second frequency other than the value of the first predetermined center frequency, so that the resulting output signal has a center frequency substantially equal to the difference of the first and second predetermined center frequencies of the first and second input signals, and substantially equal to the sum of the first and second predetermined center frequencies of the first and second input signals.

5. A single balanced mixer circuit for downconverting a single-ended input RF signal having a predetermined center frequency value to a lower center frequency value by mixing the input RF signal with a balanced local oscillator signal having a positive phase portion and a negative phase portion;

said circuit comprising;

a first MOS transistor having a gate terminal, a source terminal, a back-gate terminal and a drain terminal, said first transistor receiving the input RF signal as a first input signal through one of the gate terminal and back-gate terminal, and receiving one of the positive and negative phase portions of the local oscillator signal through the other of the gate terminal and back-gate terminal, for generating a first output signal at the drain terminal;

a second MOS transistor having a gate terminal, a source terminal, a back-gate terminal and a drain terminal, said second transistor receiving the input RF signal as a first input signal through said one of the gate terminal and back gate terminal of said second MOS transistor and receiving the other of the positive and negative phase portions of the local oscillator signal through said other of the gate terminal and the back-gate terminal of said second MOS transistor for generating a second output signal at the drain terminal of said second MOS transistor, said second output signal being opposite in phase to said first output signal; and

means connected to and for biasing the source terminals of said first and second MOS transistors.

6. The mixer circuit of claim 5, further comprising a load connected between the drain terminals of the first and second transistors and ground so that the first and second output signals comprise voltage signals.

7. A double balanced mixer circuit for downconverting a balanced input RF signal having a positive phase portion and a negative phase portion and having a predetermined center frequency value, to a lower center frequency value by mixing the RF signal with a balanced local oscillator signal having a positive phase portion and a negative phase portion, said circuit comprising:

a first MOS transistor having a gate terminal, a source terminal, a back-gate terminal and a drain terminal, said first transistor receiving as a first input signal one of the positive and negative phase portions of the input RF signal through the gate terminal, and receiving as a second input signal one of the positive and negative phase portions of the local oscillator signal through the back-gate terminal, for generating a first output signal at the drain terminal;

a second MOS transistor having a gate terminal, a source terminal, a back-gate terminal and a drain terminal, said second transistor receiving as a first input signal said one of the positive and negative phase portions of the input RF signal through said second MOS transistor gate terminal, and receiving as a second input signal the other of the positive and negative phase portions of the local oscillator signal through the back-gate terminal of said second MOS transistor, for generating a second output signal at the drain terminal of said second MOS transistor, said second output signal being opposite in phase to said first output signal;

a third MOS transistor having a gate terminal, a source terminal, a back-gate terminal and a drain terminal, said third transistor receiving as a first input signal the other of the positive and negative phase portions of the input RF signal through said third MOS transistor gate terminal, and receiving as a second input signal said other of the positive and negative phase portions of the local oscillator signal through the back-gate terminal of said third MOS transistor for generating a third output signal at the drain terminal of said third MOS transistor, said third output signal being equal in phase to said first output signal; and

a fourth MOS transistor having a gate terminal, a source terminal, a back-gate terminal and a drain terminal, said fourth transistor receiving as a first input signal said other of the positive and negative phase portions of the input RF signal through said fourth MOS transistor gate terminal, and receiving as a second input signal said one of said positive and negative phase portions of the local oscillator signal through the back-gate terminal of said fourth MOS transistor for generating a fourth output signal at the drain terminal of said fourth transistor, said fourth output signal being equal in phase to said second output signal;

the drain terminals of said first and third transistors being connected for forming from said first and third output signals a first combined output signal having a phase, and the drain terminals of said second and fourth transistors being connected for forming from said second and fourth output signals a second combined output signal having a phase opposite the phase of said first combined output signal; and

means connected to and for biasing the source terminals of said first, second, third and fourth transistors.

8. The mixer circuit of claim 7, further comprising a load connected between the drain terminals of said first, second, third and fourth transistors and a ground terminal, so that the first and second combined output signals comprise voltage signals.

9. A double balanced mixer circuit for downconverting a balanced input RF signal having a positive phase portion and a negative phase portion and having a predetermined center frequency value, to a lower center frequency value by mixing the RF signal with a balanced local oscillator signal having a positive phase portion and a negative phase portion, said circuit comprising:

a first MOS transistor having a gate terminal, a source terminal, a back-gate terminal and a drain terminal, said first transistor receiving as a first input signal one of the positive and negative phase portions of the local oscillator signal through the gate terminal, and receiving as a second input signal one of the positive and negative phase portions of the RF signal through the back-gate terminal, for generating a first output signal at the drain terminal;

a second MOS transistor having a gate terminal, a source terminal, a back-gate terminal and a drain terminal, said second transistor receiving as a first input signal said one of the positive and negative phase portions of the local oscillator signal through said second MOS transistor gate terminal, and receiving as a second input signal the other of the positive and negative phase portions of the RF signal through the back-gate terminal of said second MOS transistor, for generating a second output signal at the drain terminal of said second MOS transistor, said second output signal being opposite in phase to said first output signal;

a third MOS transistor having a gate terminal, a source terminal, a back-gate terminal and a drain terminal, said third transistor receiving as a first input signal the other of the positive and negative phase portions of the local oscillator signal through said third MOS transistor gate terminal, and receiving as a second input signal said other of the positive and negative phase portions of the RF signal through the back-gate terminal of said third MOS transistor for generating a third output signal at the drain terminal of said third MOS transistor, said third output signal being equal in phase to said first output signal; and

a fourth MOS transistor having a gate terminal, a source terminal, a back-gate terminal and a drain terminal, said fourth transistor receiving as a first input signal said other of the positive and negative phase portions of the local oscillator signal through said fourth MOS transistor gate terminal, and receiving as a second input signal said one of said positive and negative phase portions of the RF signal through the back-gate terminal of said fourth MOS transistor for generating a fourth output signal at the drain terminal of said fourth transistor, said fourth output signal being equal in phase to said second output signal;

the drain terminals of said first and third transistors being connected for forming from said first and third output signals a first combined output signal having a phase, and the drain terminals of said second and fourth transistors being connected for forming from said second and fourth output signals a second combined output signal having a phase opposite the phase of said first combined output signal; and

means connected to and for biasing the source terminals of said first, second, third and fourth transistors.

10. The mixer circuit of claim 9, further comprising a load connected between the drain terminals of said first, second, third and fourth transistors and a ground terminal, so that the first and second combined output signals comprise voltage signals.