Multi-layer circuit board and semiconductor flip chip connection

• US 5,768,109 A
• Filed: 07/22/1996
• Issued: 06/16/1998
• Est. Priority Date: 06/26/1991
• Status: Expired due to Term

• Current Assignee: Hughes Electronics Corporation (Rtx Corporation)
• Original Assignee: Hughes Electronics Corporation (Rtx Corporation)
• Inventors: Shoda, Craig K., Gulick, Jon J.
• Primary Examiner(s): SPARKS, DONALD ALAN
• Application Number:
  US08/681,136
• Time in Patent Office: 694 Days
• Field of Search: 174/260, 174/261, 174/35 R, 228/179.1, 228/180.1, 228/180.21, 228/180.22, 257/700, 257/723, 257/724, 257/728, 257/659, 257/778, 257/779, 257/735, 257/738, 361/760, 361/767, 361/770-774, 361/777, 361/780, 361/782, 361/783, 361/792-795, 439/68, 439/82, 439/83, 439/179, 439/607, 429/901, 333/246, 333/247, 437/209, 437/183
• US Class Current: 361/794
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 2924/01077 Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/1423 Monolithic Microwave Integrated Circuit [MMIC]
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H05K 1/0298 Multilayer circuits
• CPC Class Codes: H05K 2201/09072 Hole or recess under component or special relationship between hole and component
• CPC Class Codes: H05K 2201/10674 Flip chip

Abstract

A multi-layer circuit board (11) has a cofired ceramic with a configuration of circuit traces (27) extending though differing layers of the multi-layer circuit board (11) to facilitate mountable conductive contact with semiconductor flip chips (13). Via holes (23) are precisely formed in the multi-layer circuit board (11) and are filled with solder or conductive epoxy. Semiconductor chips (13) have an array of metallic posts (19) alignable with the holes (23) and are mounted upon the upper surface of the multi-layer circuit board (11) in plug fashion. An aperture (25) may be formed in multi-layer circuit board (11) directly below each semiconductor chip (13) for protection of the circuitry on semiconductor chip (13) from contact with multi-layer circuit board (11). The via holes (23) and transmission line structure of the circuit board (11) are precisely formed to achieve a desired characteristic impedance.

Claims

1. A circuit comprising:

a multi-layer circuit board including a substrate having a top face and conductive traces extending through its volume between differing layers, and a series of holes extending from a surface of the circuit board into its volume a sufficient length through one or more of said layers to expose a portion of said conductive traces associated therewith, wherein said conductive traces include signal transmission lines and ground lines configured so as to provide a desired characteristic impedance in selected signal transmission lines and said holes are precisely located to achieve said desired characteristic impedance through the selected signal transmission lines so as to provide predetermined signal transmission performance for microwave or millimeter wave frequencies, wherein said multi-layer circuit board comprises a cofired ceramic substrate having a plurality of dielectric layers which separate the signal transmission lines from the ground via controlled thickness of said dielectric layers;

a conductive material in each of said series of holes and contacting the exposed portion of the conductive traces;

a semiconductor flip chip having a series of metallic bumps extending from input-output pads and connected to circuitry on the chip and extending into said holes, the metallic bumps being in contact with said conductive material thereby making electrical connection to the traces via said conductive material; and

at least one cavity formed through one or more layers of said board, said cavity having edges adjacent said holes and a volume beneath said chip for providing an air gap with a selected thickness for protecting circuitry on said chip and further improving high frequency signal operations.

2. The circuit of claim 1 wherein said circuit traces form a stripline circuit configuration.

3. The circuit of claim 1 wherein said circuit traces form a microstrip circuit configuration.

4. The circuit of claim 1 wherein said each of said holes are laser drilled.

5. The circuit of claim 1 where said conductive material comprises solder.

6. The circuit of claim 1 where said conductive material comprises conductive epoxy.

7. The circuit of claim 1 wherein said metallic bumps comprise electrodeposited metal.

8. The circuit of claim 1 wherein a dielectric passivation layer is connected to said semiconductor chip which extends between said semiconductor chip and said circuit board, said dielectric layer being formed close to said metallic bumps so as to prevent the flow of said conductive material from said holes.

9. The circuit of claim 1 further comprising a plurality of said semiconductor chips on said circuit board.

10. The circuit of claim 1 wherein said conductive traces have said exposed portion located on a bottom side of the associated hole.

11. The circuit of claim 1 wherein said flip chip has a bottom face lying substantially flush against portions of the top face of the circuit board.

12. The circuit of claim 1 wherein said series of metallic bumps extend substantially the same distance from said chip such that said bumps are electrically connected to said conductive traces via controlled volume of said conductive material.

13. The circuit of claim 1 wherein said series of metallic bumps include top side surfaces, bottom side surfaces and a bottom end wherein said top side surfaces are essentially free from contact with said conductive material to ensure that said conductive material does not escape from said holes upon displacement by said bumps.

14. The circuit of claim 1 wherein a dielectric passivation layer is connected to said semiconductor chip along a perimeter of a bottom surface thereof to form an insulation layer between said chip and said circuit board while leaving a center portion of said chip exposed to said cavity.

15. The circuit of claim 1 wherein a dielectric passivation ring encircles each of said bumps and is connected to said semiconductor chip.

16. The circuit of claim 1 wherein said series of holes have a diameter, depth and location in said circuit board corresponding to said desired characteristic impedance.

17. A microwave/millimeter wave semiconductor flip chip to circuit board circuit comprising:

a multi-layer circuit board including a cofired ceramic substrate having a plurality of dielectric layers and conductive traces extending through its volume and between differing dielectric layers of the multi-layer circuit board, and a series of holes extending from a top surface of the circuit board into its volume a sufficient length through one or more of said layers to expose a portion of the conductive traces providing signal transmission lines and ground lines, and wherein said holes may extend to differing levels within the multi-layer circuit board to facilitate routing of said conductive traces;

a conductive filler material disposed in each of said series of holes and which contacts the exposed portion of the conductive traces thereby forming an electrical connection therewith;

a semiconductor flip chip having a series of metallic bumps extending from input-output pads thereon and having circuitry for operating with signals having frequencies in the microwave or millimeter wave range, said series of metallic bumps partially extending directly into said series of holes of said circuit board such that the metallic bumps contact the conductive material thereby making electrical connection to the conductive traces and

at least one cavity formed through one or more layers of said board, said cavity having edges adjacent said holes and a volume beneath said chip for providing an air gap with a selected thickness for protecting circuitry on said chip and further improving high frequency signal operations;

wherein select signal transmission lines are arranged relative to said ground lines so as to achieve a desired characteristic impedance.

18. The circuit of claim 17 wherein said circuit traces form a stripline circuit configuration.

19. The circuit of claim 17 wherein said circuit traces form a microstrip circuit configuration.

20. The circuit as defined in claim 17 further comprising a controlled thickness cavity extending through one or more layers of said circuit board, said controlled thickness cavity providing a controlled height air gap between said circuit board and said semiconductor flip chip for purposes of preventing damage to circuitry on said chip and further enhancing high frequency signal operations.

21. The circuit as defined in claim 17 wherein said conductive traces have said exposed portion located on a bottom side of the associated hole.