Reciprocating converter

• US 5,768,118 A
• Filed: 12/31/1996
• Issued: 06/16/1998
• Est. Priority Date: 05/01/1996
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Compaq Computer Corporation (HP Inc.)
• Inventors: Ho, J. Howard, Faulk, Richard A.
• Primary Examiner(s): Tso, Edward
• Assistant Examiner(s): Riley, Shawn
• Application Number:
  US08/777,786
• Time in Patent Office: 532 Days
• Field of Search: 363/20, 363/21, 363/17, 363/41, 363/131, 363/18, 363/19, 363/72, 323/288
• US Class Current: 363/72
• CPC Class Codes: H02M 1/44 Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
• CPC Class Codes: H02M 3/33576 having at least one active switching element at the secondary side of an isolation transformer

Abstract

A power converter which transfers energy from an output circuit coupled to a secondary winding of a power transformer to an input circuit coupled to a primary winding of the power transformer in order to reduce the power loss and electromagnetic interference (EMI) originating from a primary switch. The reciprocating action of the converter is accomplished by placing the series switched path of a secondary switch in parallel with a diode in the output circuit. A control circuit is coupled to the primary switch and the secondary switch which allows the inherent capacitance of each switch to discharge before turning on the respective switch, thereby reducing the EMI and power losses occurring at these switches. The control circuit includes feedback and feedforward voltage control of the switching duty cycle. The control circuit varies the energy transferred from the output circuit to the input circuit according to changes in the accumulated charge on the primary switch.

Claims

1. A method of operating a power converter, comprising the steps of:

(a.) ramping up current in a first direction through a primary winding of a transformer;

(b.) opening a first switch which is in series with said primary winding, to obstruct current through said primary winding and thereby drive current through a secondary winding of said transformer which is inductively coupled to said primary winding;

(c.) closing a second switch which is in series with said secondary winding, to permit said secondary winding to pass current in a first direction to charge up an output capacitor;

(d.) holding said second switch closed for long enough so that current in said secondary winding becomes zero, and thereafter said output capacitor drives current through said secondary winding in a second direction which is opposite to said first direction;

(e.) opening said second switch while said secondary winding is passing current in said second direction, to thereby drive current through said primary winding in a second direction which is opposite to said first direction while said first switch remains open;

whereby said step (e.) recovers energy stored on the parasitic capacitance of said first switch.

2. The method of claim 1, wherein said second switch is shunted by a diode which passes current in said first direction.

3. The method of claim 1, further comprising the subsequent step (f.) of turning said first transistor on, after said step (e.), only after the magnitude of the voltage across said first transistor has decreased by at least half.

4. The method of claim 1, further comprising the subsequent step (f.) of turning said first transistor on, after said step (e.), only after the magnitude of the voltage across said first transistor has decreased by at least 75%.

5. The method of claim 1, further comprising the subsequent step (f.) of turning said first transistor on, after said step (e.), only after the magnitude of the voltage across said first transistor has decreased to a minimum voltage which is less than 50 Volts.

6. The method of claim 1, further comprising the subsequent step (f.) of turning said first transistor on, after said step (e.), only after the magnitude of the current across said primary winding has reached approximately zero.

7. The method of claim 1, wherein said first switch is shunted by a capacitive snubber circuit.

8. The method of claim 1, wherein said first and second switches are both field-effect transistors.

9. The method of claim 1, wherein said first and second switches are both vertical DMOS transistors.

10. A power converter circuit comprising:

a transformer having primary and secondary windings inductively coupled together;

a first switching transistor connected to increase current in a first sense through said primary winding when said transistor is on, and to obstruct current through said primary winding when said transistor is off;

an output capacitor having a first terminal operatively connected to a first terminal of said secondary winding, and a second terminal operatively connected to a second terminal of said secondary winding through a second switching transistor; and

control circuitry connected to turn on said second transistor during at least some times when said first transistor is off, and to keep said second transistor continuously on thereafter until the direction of current flowing therethrough has reversed, and thereafter to turn off said second transistor to thereby drive current through said primary winding in a second sense which is opposite to said first sense while said first transistor remains off;

whereby energy stored on the parasitic capacitance of said first switch is recovered.

11. The circuit of claim 10, wherein said second transistor is shunted by a diode which passes current in said first direction.

12. The circuit of claim 10, wherein said control circuitry turns said first transistor on, while current is flowing through said primary winding in said second sense, only after the magnitude of the voltage across said first transistor has decreased by at least half.

13. The circuit of claim 10, wherein each said transistor is a unipolar device.

14. The circuit of claim 10, wherein said first transistor is shunted by a capacitive snubber circuit.

15. The circuit of claim 10, wherein said first and second transistors are both field-effect transistors.

16. The circuit of claim 10, wherein said first and second transistors are both vertical DMOS transistors.

17. A computer system comprising:

a user input device;

a microprocessor operatively connected to detect inputs from said input device;

memory which is read/write accessible by said microprocessor;

a display operatively connected to display data generated by said microprocessor;

a power connection for drawing power from AC mains, and a power supply connected to said power connection;

wherein said power supply comprises

a transformer having primary and secondary windings inductively coupled together;

a first switching transistor connected to increase current in a first sense through said primary winding when said transistor is on, and to obstruct current through said primary winding when said transistor is off;

an output capacitor having a first terminal operatively connected to a first terminal of said secondary winding, and a second terminal operatively connected to a second terminal of said secondary winding through a second switching transistor; and

control circuitry connected to turn on said second transistor during at least some times when said first transistor is off, and to keep said second transistor continuously on thereafter until the direction of current flowing therethrough has reversed, and thereafter to shut off said second transistor to drive current through said primary winding in a second sense which is opposite to said first sense while said first transistor remains off;

whereby energy stored on the parasitic capacitance of said first switch is recovered.

18. The circuit of claim 17, wherein said second transistor is shunted by a diode which passes current in said first direction.

19. The circuit of claim 17, wherein each said transistor is a unipolar device.

20. The circuit of claim 17, wherein said first transistor is shunted by a capacitive snubber circuit.

21. The circuit of claim 17, wherein said first and second transistors are both field-effect transistors.

22. The circuit of claim 17, wherein said first and second transistors are both vertical DMOS transistors.

23. The circuit of claim 17, wherein said control circuitry turns said first transistor on, while current is flowing through said primary winding in said second sense, only after the magnitude of the voltage across said first transistor has decreased by at least half.