Method of cell contouring to increase device density

• US 5,768,146 A
• Filed: 03/28/1995
• Issued: 06/16/1998
• Est. Priority Date: 03/28/1995
• Status: Expired due to Term

• Current Assignee: Donald R. Roberts
• Original Assignee: Intel Corporation
• Inventors: Jassowski, Michael
• Primary Examiner(s): LOUIS JACQUES, JACQUES H
• Application Number:
  US08/412,291
• Time in Patent Office: 1,176 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 364/578, 257/202-208, 257/370, 257/362, 257/497, 257/923, 257/210, 257/211, 326/21, 326/41, 326/50
• US Class Current: 716/120
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Abstract

A layout arrangement which provides a contouring of cells that allows the individual rectangular cell boundaries to overlap each other to a point at which individual device edges abut one another thereby utilizing die area which is normally lost to use. In order to attain this result, a new cell contour boundary is described about each cell at the edge of each individual device adjacent the exterior of the cell at a distance at which other cells may abut without disturbing the operation of the cell. Then, computer implemented processes are applied to cause the cells to fit abutting the newly described boundaries.

Claims

1. A computer implemented method for positioning standard cells on a semiconductor substrate comprising the steps of:

determining a minimum boundary surrounding each standard cell to which circuit devices may approach without significantly disturbing the operation characteristics of the standard cell;

positioning the standard cells in substantially parallel rows on the semiconductor substrate as defined by substantially parallel busing conductors, at least some of the rows defined by a single busing conductor, wherein consecutive rows of single busing conductors are of alternating polarity; and

adjusting the positions of the standard cells to fit as closely as possible to standard cells in adjacent parallel rows along edges of the minimum boundaries surrounding each cell,

wherein at least one of the standard cells in at least one of the substantially parallel rows has a different height than that of another standard cell in that same substantially parallel row.

2. The computer implemented method of claim 1 wherein each of busing conductor provides power to at least one of the substantially parallel rows of the standard cells.

3. A computer implemented method for positioning standard cells on a semiconductor substrate comprising the steps of:

(a) determining a minimum boundary surrounding each standard cell to which circuit devices may approach without significantly disturbing the operation characteristics of the standard cell;

(b) positioning the standard cells in substantially parallel rows on the semiconductor substrate as defined by substantially parallel busing conductors, at least some of the rows defined by a single busing conductor, wherein consecutive rows of single busing conductors are of alternating polarity, the substantially parallel rows being in a first direction, the standard cells in each of the substantially parallel rows optionally having different heights in a second direction which is approximately perpendicular to the first direction; and

(c) adjusting the positions of the standard cells to fit as closely as possible to standard cells in adjacent parallel rows along edges of the minimum boundaries surrounding each cell.

4. The computer implemented method of claim 3 wherein at least one standard cell of one of the substantially parallel rows has a different height in the second direction than another standard cell of the same substantially parallel row.

5. The computer implemented method of claim 3 wherein each busing conductor provides power to at least one of the substantially parallel rows of the standard cells.

6. A computer implemented method for positioning standard cells on a semiconductor substrate comprising the steps of:

(a) determining a minimum boundary surrounding each standard cell to which circuit devices may approach without significantly disturbing the operation characteristics of the standard cell;

(b) positioning the standard cells in substantially parallel rows on the semiconductor substrate as defined by substantially parallel busing conductors, at least some of the rows defined by a single busing conductor, wherein consecutive rows of single busing conductors are of alternating polarity, the substantially parallel rows being in a first direction, each of the standard cells in each of the substantially parallel rows having a height in a second direction which is approximately perpendicular to the first direction, at least one standard cell in at least one of the substantially parallel rows having a different height than that of another standard cell in that same substantially parallel row; and

(c) adjusting the positions of the standard cells to fit as closely as possible to standard cells in adjacent parallel rows along edges of the minimum boundaries surrounding each cell.

7. The computer implemented method of claim 6 wherein busing conductor provides power to at least one of the substantially parallel rows of the standard cells.

8. A method for positioning standard cells on a semiconductor substrate comprising the steps of:

(a) determining a minimum boundary surrounding each standard cell to which circuit devices may approach while maintaining the electrical integrity of the standard cell;

(b) positioning the standard cells in substantially parallel rows on the semiconductor substrate as defined by substantially parallel busing conductors, at least some of the rows defined by a single busing conductor, wherein consecutive rows of single busing conductors are of alternating polarity, the substantially parallel rows being in a first direction, each of the standard cells in each of the substantially parallel rows having a height in a second direction which is approximately perpendicular to the first direction, at least one standard cell in at least one of the substantially parallel rows having a different height than that of another standard cell in that same substantially parallel row; and

(c) adjusting the positions of the standard cells to fit as closely as possible to standard cells in adjacent parallel rows along edges of the minimum boundaries surrounding each cell.