Method of simulating AC timing characteristics of integrated circuits

• US 5,768,159 A
• Filed: 05/02/1996
• Issued: 06/16/1998
• Est. Priority Date: 05/02/1996
• Status: Expired due to Fees

• Current Assignee: Nortel Networks Limited (Nortel Networks Corporation)
• Original Assignee: Northern Telecom Limited (Nortel Networks Corporation)
• Inventors: Sankey, Wayne R., Belkadi, Mustapha
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): FREJD, RUSSELL WARREN
• Application Number:
  US08/643,136
• Time in Patent Office: 775 Days
• Field of Search: 395/500, 395/555, 395/250, 371/25, 371/23, 371/22.1, 371/27, 307/279, 364/578, 364/489, 375/107, 324/617
• US Class Current: 703/19
• CPC Class Codes: G01R 31/3016 Delay or race condition test, e.g. race hazard test
• CPC Class Codes: G01R 31/318314 Tools, e.g. program interfaces, test suite, test bench, simulation hardware, test compiler, test program languages simulation software G01R31/318357; emulators G06F11/261
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A method of simulating AC timing characteristics at the pins of a device in of an application specific integrated circuit (ASIC) design is presented. The approach is fully automatic and is generalized, in the sense that both positive and negative Setup and Hold times and Propagation delays can be captured. The approach allows each bit of a data bus to be treated individually so as to be able to identify the worst case Setup time, Hold time and Propagation delay. Measurement is carried out in parallel for all data inputs and outputs. The need for manual intervention is eliminated and considerably reduces simulation time. Delay files are used through a call from a test bench, and the same testbench can be run on different delay information, namely pre-layout or post-layout delays.

Claims

1. A method of simulating AC timing characteristics of an integrated circuit comprising:

identifying a first flip flop associated with an input of the integrated circuit, the flip flop having a clock input and a data input;

applying a clock reference signal to the clock input of the flip-flop, and applying a data input signal to the data input of the flip-flop, the data input signal edge having a specific time delay relative to the clock signal active edge, thereby generating a known logic value at an output of the flip-flop;

then successively applying the clock reference signal and a data input signal while changing the specific time delay between the clock reference signal active edge and data input signal edge thereby relatively moving the data input signal edge and the active edge of the clock reference signal until an unknown logic value X, characteristic of an X condition, is observed at the output of the flip-flop,

and calculating one of the Setup time and Hold time from the specific delay time between the clock reference signal and data input signal for the time values immediately preceding those when the X condition is generated.

2. A method of simulating AC timing characteristics of an integrated circuit comprising:

identifying a first flip flop associated with an input of the integrated circuit, the flip flop having a clock input and a data input;

applying a clock reference signal to the clock input of the flip-flop, and applying a data input signal to the data input of the flip-flop, the data input signal edge having a specific time delay relative to the clock signal active edge, thereby generating a known logic value at an output of the flip-flop;

then successively applying the clock reference signal and a data input signal while changing the specific time delay between the clock reference signal active edge and data input signal edge thereby relatively moving the data input signal edge and the active edge of the clock reference signal until an unknown logic value X, characteristic of an X condition, is observed at the output of the flip-flop,

and then calculating a Setup time, wherein the data edge is moved relative to the active edge of the clock to decrement the specific delay time between the active edge of the clock reference signal and the data signal edge, and a Setup time measurement is made after each decrement of the data edge, and when the X condition is observed, the Setup time preceding the one causing the X condition is taken as the correct minimum Setup time,

wherein the Setup time is calculated by

space="preserve" listing-type="equation">Setup=-(Data.sub.edge -(Clkref.sub.a +Clkref.sub.period /2))

where,

Data_edge =data edge occurrence time;

Clkref_a =reference clock active edge occurrence time; and

Clkref_period =period of the reference clock.

3. A method according to claim 2 wherein the Setup time is measured for both the rising edge of the data signal and the falling edge of the data signal.

4. A method according to claim 2 wherein the flip flop under consideration is rising edge triggered and the active edge of the clock is a falling edge.

5. A method according to claim 2 wherein the flip flop under consideration is falling edge triggered and the active edge of the clock is a rising edge.

6. A method of simulating AC timing characteristics of an integrated circuit comprising:

identifying a first flip flop associated with an input of the integrated circuit, the flip flop having a clock input and a data input;

applying a clock reference signal to the clock input of the flip-flop, and applying a data input signal to the data input of the flip-flop, the data input signal edge having a specific time delay relative to the clock signal active edge, thereby generating a known logic value at an output of the flip-flop;

then successively applying the clock reference signal and a data input signal while changing the specific time delay between the clock reference signal active edge and data input signal edge thereby relatively moving the data input signal edge and the active edge of the clock reference signal until an unknown logic value X, characteristic of an X condition, is observed at the output of the flip-flop, and then calculating a Hold time, wherein the active edge of the clock is moved relative to the data signal edge to decrement the specific delay time between the active edge of the clock reference signal and the data signal edge, and a Hold time measurement is made after each decrement of the clock edge, and when the X condition is observed, the Hold time preceding that Hold time causing the X condition is taken as the correct Hold time for that data signal,

wherein the Hold time is calculated by;

space="preserve" listing-type="equation">Hold=-(Clkref.sub.a -(Data.sub.edge +Data.sub.period /2))

where,

Clkref_a =reference clock active edge occurrence time,

Data_edge =data edge occurrence time;

Data_period =period of the data signal.

7. A method according to claim 6 wherein relative to the active edge of clock, the Hold time is measured for both the rising edge of data signal and for the falling edge of the data signal.

8. A method according to claim 6 wherein the flip flop under consideration is rising edge triggered and the active edge of clock is a falling edge.

9. A method according to claim 6 wherein the flip flop under consideration is falling edge triggered and the active edge of clock is a rising edge.

10. A method of simulating AC timing characteristics of an integrated circuit comprising:

identifying a first flip flop associated with an input of the integrated circuit having a clock input, a data input, and an output;

applying a clock reference signal to the clock input of the flip-flop, and applying a data input signal to the data input of the flip-flop with a specific time delay between the edge of the data signal and to the active edge of the clock input signal, thereby generating a known logic value at the output of the flip-flop;

observing the active edge of the reference clock and the changing edge of the output data signal, and measuring a propagation delay given by

space="preserve" listing-type="equation">Propagation delay=Data.sub.edge -Clkref.sub.a,

where,

Data_edge =occurrence time of the changing data edge;

Clkref_a =occurrence time of the reference clock active edge.

11. A method according to claim 10 wherein the flip-flop under consideration is rising edge triggered, and the propagation delay is measured at the occurrence of a falling edge of the reference clock whereby both positive and negative propagation delays can be captured for both the rising and falling edges of the output data.

12. A method according to claim 10 wherein the flip-flop under consideration is falling edge triggered, and the propagation delay is measured at the occurrence of a rising edge of the reference clock whereby both positive and negative propagation delays can be captured for both the rising and falling edges of the output data.

13. A method of simulating AC timing characteristics of an integrated circuit to determine Setup and Hold times and Propagation delay, comprising:

identifying a first flip flop associated with an input of the integrated circuit and having a clock input and a data input;

applying a clock reference signal to the clock input of the flip-flop, and applying a data input signal to the data input of the flip-flop, the data input signal edge having a specific time delay relative to the clock input signal edge, thereby generating a known logic value at an output of the flip-flop;

then successively applying the clock reference signal and a data input signal while decrementing the specific time delay between the the clock reference signal and data input signal thereby relatively moving the data edge and the active edge of the clock signal until an unknown logic value X, characteristic of an X condition, is observed at the flip flop output,

determining the Setup time by moving the data edge relative to the active edge of the clock and making a Setup time measurement after each decrement of the data edge, and when the X condition is observed, the Setup time preceding the one causing the X condition is taken as the correct minimum Setup time, wherein the Setup time is calculated by

space="preserve" listing-type="equation">Setup=-(Data.sub.edge -(Clkref.sub.a +Clkref.sub.period /2))

where,

Data_edge =data edge occurrence time;

Clkref_a =reference clock active edge occurrence time; and

Clkref_period =period of the reference clock;

determining the Hold time by moving the active edge of the clock relative to the data edge and making a Hold time measurement after each decrement of the clock edge, and when the X condition is observed, the Hold time preceding that Hold time causing the X condition is taken as the correct Hold time for that data signal wherein the Hold time is calculated by;

space="preserve" listing-type="equation">Hold=-(Clkref.sub.a -(Data.sub.edge +Data.sub.period /2)),

where

Clkref_a =reference clock active edge occurrence time,

Data_edge =data edge occurrence time; and

Data_period =period of the data signal,

and,

measuring the propagation delay by steps comprising;

applying a clock reference signal Clkref to the clock input of the flip-flop, and applying a data input signal to a data input of the flip-flop, with a specific time delay relative to the clock input, thereby generating a known logic value at an output of the flip-flop;

observing the active edge of the reference clock and the changing edge of the output data signal, and measuring a propagation delay given by

space="preserve" listing-type="equation">Propagation delay=Data.sub.edge -Clkref.sub.a

where,

Data_edge =occurrence time of the changing data edge;

Clkref_a =occurrence time of the reference clock active edge.