Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping

• US 5,768,192 A
• Filed: 07/23/1996
• Issued: 06/16/1998
• Est. Priority Date: 07/23/1996
• Status: Expired due to Term

• Current Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Original Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Inventors: Eitan, Boaz
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US08/681,430
• Time in Patent Office: 693 Days
• Field of Search: 365/182, 365/184, 365/185.01, 365/189.12, 365/185.24, 365/185.28, 365/185.14, 365/185.26
• US Class Current: 365/185.24
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors

Abstract

A novel apparatus for and method of programming and reading a programmable read only memory (PRON) having a trapping dielectric sandwiched between two silicon dioxide layers is disclosed that greatly reduces the programming time of conventional PROM devices. Examples of the trapping dielectric are silicon oxide-silicon nitride-silicon oxide (ONO) and silicon dioxide with buried polysilicon islands. A nonconducting dielectric layer functions as an electrical charge trapping medium. This charge trapping layer is sandwiched between two layers of silicon dioxide acting as an electrical insulator. A conducting gate layer is placed over the upper silicon dioxide layer. The memory device is programmed in the conventional manner, using hot electron programming, by applying programming voltages to the gate and the drain while the source is grounded. Hot electrons are accelerated sufficiently to be injected into the region of the trapping dielectric layer near the drain. The device, however, is read in the opposite direction from which it was written, meaning voltages are applied to the gate and the source while the drain is grounded. For the same applied gate voltage, reading in the reverse direction greatly reduces the potential across the trapped charge region. This permits much shorter programming times by amplifying the effect of the charge trapped in the localized trapping region.

Claims

1. A programmable read only memory (PROM) device, comprising:

a semiconducting substrate of a first conductivity type;

a source, said source comprising a region of said semiconducting substrate doped to have a conductivity opposite that of said semiconducting substrate;

a drain, spaced from said source, said drain comprising a portion of said semiconducting substrate doped to have a conductivity opposite that of said semiconducting substrate,a channel being formed in the space between said source and said drain within said semiconducting substrate;

a first insulating layer overlaying and covering said channel portion of said semiconducting substrate;

a nonconducting charge trapping layer formed on and overlaying said first insulating layer;

a second insulating layer formed on and overlaying said nonconducting charge trapping layer;

a gate, said gate comprising an electrically conductive material formed on and overlaying said second insulating layer; and

wherein said charge trapping layer is formed so as to receive and retain electrons injected into said charge trapping layer in a charge storage region close to said drain forming a bit, the quantity of electrons so stored being selected so as to provide said cell with a first threshold voltage greater than first selected value when said memory cell is read in a first direction opposite to that in which it was programmed and to Provide said cell with a second threshold voltage when said memory cell is read in a second direction which is the same direction in which it was programmed, said second threshold voltage being substantially lower than said first threshold voltage.

2. The memory device according to claim 1, wherein a lower limit for the voltage applied to said gate during reading is the voltage at which sufficient inversion is generated in the channel whereby the unprogrammed state can be sensed, an upper limit for the voltage applied to said gate during reading is the voltage at which the voltage across a region of said channel beneath the trapped charge in said charge storage region is below the voltage applied to said source during reading.

3. The memory device according to claim 1, wherein programming said bit comprises applying programming voltages to said drain and said gate, grounding said source and measuring the resulting channel current and wherein reading said bit comprises applying reading voltages to said source and said gate, grounding said drain and measuring the resulting channel current reading;

4. The memory device according to claim 1, wherein said first and second insulating layers comprise silicon dioxide.

5. The memory device according to claim 1, wherein said charge trapping layer comprises silicon nitride.

6. The memory device according to claim 1, wherein said charge trapping layer comprises silicon dioxide with buried polysilicon islands.

7. The memory device according to claim 1, wherein said semiconducting substrate comprises P-type semiconductor material.

8. The memory device according to claim 1, wherein said source and said drain comprise N+ semiconductor.

18. The memory cell according to claims 1 or 9, wherein the amount of charge stored in said region of trapped charge for said bit in said nonconducting charge trapping layer is such that the change in threshold voltage for reading in the reverse direction relative to reading in the forward direction is greater than a factor of ten.

19. The memory cell according to claims 1 or 9, wherein the amount of charge stored in said region of trapped charge for said bit in said nonconducting charge trapping layer is such that the change in threshold voltage for reading in the reverse direction relative to reading in the forward direction is greater than a factor of five.

20. The memory cell according to claims 1 or 9, wherein the amount of charge stored in said region of trapped charge for said bit in said nonconducting charge trapping layer is such that the change in threshold voltage for reading in the reverse direction relative to reading in the forward direction is greater than a factor of two.

21. The memory cell according to claims 1 or 9, wherein the amount of charge stored in said region of trapped charge for said bit in said nonconducting charge trapping layer is such that the change in threshold voltage for reading in the reverse direction relative to reading in the forward direction is greater than a factor of one and one half.

22. The memory cell according to claims 1 or 9, wherein said charge trapping layer comprises silicon dioxide with impurities therein.

9. A programmable read only memory (PROM) device, comprising:

semiconducting substrate of a first conductivity type;

a source, said source comprising a region of said semiconducting substrate doped to have a conductivity opposite that of said semiconducting substrate;

a drain, spaced from said source, said drain comprising a region of said semiconducting substrate doped to have a conductivity opposite that of said semiconducting substrate, a channel being formed between said source and said drain within said semiconducting substrate;

a first insulating layer overlaying and covering said channel portion of said semiconducting substrate;

a nonconducting charge trapping layer formed on and overlaying said first insulating layer;

a second insulating layer formed on and overlaying said nonconducting charge trapping layer;

a gate, said gate comprising an electrically conductive material formed on and overlaying said second insulating layer;

wherein said cell is adapted to receive and retain electrons injected into said nonconducting charge trapping layer in a region close to said source forming a bit; and

wherein said memory is adapted to be read in a direction opposite to that in which it was programmed, such that a lower limit for the voltage applied to said gate during reading said bit is the voltage at which sufficient inversion is generated in said channel whereby an unprogrammed state can be sensed, an upper limit for the voltage applied to said gate during reading said bit is the voltage at which the voltage across a region of said channel beneath the trapped charge in said charge storage region is below the voltage applied to said source during reading said bit.

10. The memory device according to claim 9, wherein said bit of said memory cell is adapted to be programmed by applying programming voltages to said drain and said gate, grounding said source and measuring the resulting channel current and wherein said bit of said memory cell is adapted to be read by applying reading voltage to said source and said gate, grounding said drain and measuring the resulting channel current.

11. The memory device according to claim 9, wherein said first and second insulating layers comprise silicon dioxide.

12. The memory device according to claim 9, wherein said charge trapping layer comprises silicon nitride.

13. The memory device according to claim 9, wherein said charge trapping layer comprises silicon dioxide with buried polysilicon islands.

14. The memory device according to claim 9, wherein said semiconducting substrate comprises P-type semiconductor material.

15. The memory device according to claim 9, wherein said source and said drain comprise N+ semiconductor material.

16. A method of programming and reading a programmable read only memory (PROM) cell, said PROM cell having a semiconducting substrate, source, drain with a channel therebetween and a gate above said channel separated therefrom by a nonconducting charge trapping material sandwiched between first and second silicon dioxide layers, said method comprising the steps of:

programming in a forward direction by injecting electrical charge into said charge trapping material utilizing hot electron injection for a sufficient time that electrical charge becomes trapped asymmetrically in a charge trapping region of said charge trapping material close to said drain forming a bit, said electric charge being injected until the threshold voltage of said memory gate reaches a predetermined level when said memory cell is read in the reverse direction from which it was programmed;

said asymmetrical charge injection for said bit being generated by applying programming voltages to said drain and said gate and grounding said source; and

reading in reverse direction by applying read voltages to said source and said gate and grounding said drain, and subsequently sensing whether or not current flows through said memory cell from said source to said drain.

17. The method according to claim 16, wherein a lower limit for said reading voltage applied to said gate during said step of reading said bit is the voltage at which sufficient inversion is generated in said channel whereby the unprogrammed state can be sensed, an upper limit for said reading voltage applied to said gate during said step of reading said bit is the voltage at which the voltage across a region of said channel beneath the trapped charge in said storage is below the voltage applied to said source during, reading of said bit.

23. A programmable read only memory (PROM) cell, comprising:

a semiconductor substrate of a first conductivity type containing therein a source region and a drain region each of a second conductivity type opposite to said first conductivity type and separated from each other by a channel region normally of said first conductivity type;

a dielectric formed over said channel region, said dielectric being capable of holding selected charge in a portion thereof above and adjacent to said drain region, said dielectric including a first layer of silicon oxide, a second layer of silicon oxide and a charge trapping material formed between said first layer of silicon oxide and said second layer of silicon oxide;

a gate comprising an electrically conductive layer formed on and overlaying said dielectric;

a first voltage source capable of being connected to said drain, a second voltage source capable of being connected to said gate and a third voltage source capable of being connected to said source; and

a control both for causing said first voltage source to apply a first voltage to said drain, said second voltage source to apply a second voltage to said gate, and said third voltage source to apply a third voltage to said source, thereby to cause electrons to be injected by hot electron injection into said portion of said dielectric and for causing said first voltage source to apply a fourth voltage to said drain, said second voltage source to apply a fifth voltage to said gate and said third voltage source to apply a sixth voltage to said source thereby to cause said memory cell to read in the reverse direction from the direction in which the cell was programmed.

24. The memory cell according to claim 23, wherein said charge trapping material comprises silicon nitride, said layer of silicon nitride being of such a thickness as to receive and retain a selected charge in a localized portion of said silicon nitride, and wherein the remainder of said dielectric is adapted to assist in retaining the charge in the silicon nitride in said portion of the silicon nitride in which the charge is formed.

25. The memory cell according to claim 24 wherein said first layer of silicon oxide is formed between said silicon nitride layer and said semiconductor substrate and said second layer of silicon oxide is formed between said silicon nitride layer and said gate.

26. The memory cell according to claim 23 wherein said semiconductor substrate comprises silicon and said first layer of silicon oxide is formed by thermally oxidizing said semiconductor substrate.

27. The memory cell according to claim 23, wherein said charge trapping region comprises silicon nitride, said second layer of silicon oxide is formed at least in part by thermally oxidizing a top portion of the layer of said silicon nitride.

28. The memory cell according to claim 23, wherein said second layer of silicon oxide comprises at least a portion formed from the deposition of silicon dioxide.

29. The memory cell according to claim 23 wherein said second layer of silicon oxide is formed at least in part by die deposition of silicon dioxide from TEOS.

30. The memory cell according to claim 24, wherein said second layer of silicon oxide is formed by at least one of the following:

thermal oxidation of the top surface of said silicon nitride layer, the chemical vapor deposition of silicon dioxide from selected reactants or the deposition of silicon dioxide from the decomposition of TEOS.

31. The memory cell according to claim 23, wherein said dielectric comprises a selected layer of silicon dioxide formed with selected pockets of polycrystalline silicon dispersed therein, said pockets of polycrystalline silicon being capable of retaining a charge lodged in said polycrystalline silicon.

32. The memory cell according to claim 23, wherein said dielectric comprises selected impurities which are capable of retaining a charge.

33. The memory cell according to claim 23, wherein said dielectric comprises a pocket of polycrystalline silicon located adjacent the drain region of said cell, said pocket of polycrystalline silicon being capable of storing trapped charges.

34. The memory cell according to claim 23, wherein said dielectric comprises at least a portion thereof formed by depositing silicon dioxide in a silicon rich environment such that precipitates of silicon form randomly but are dispersed throughout a portion of the silicon dioxide layer, said precipitates of silicon serving to hold trapped charge injected into said portion of said silicon dioxide layer.

35. A semiconductor memory cell, comprising:

a substrate of a first conductivity type including a source region of a second conductivity type opposite the said first conductivity type and a drain region of said second conductivity type, said source and drain being respectively spaced from each other by a channel region normally of said first conductivity type formed therebetween;

dielectric capable of holding an electrical charge in a charge trapping region thereof formed over said channel region;

a conductive gate formed over said dielectric;

means for applying a first voltage to said source region and a second voltage to said gate region thereby to cause electrons to be lodged on and stored in said charge trapping region associated with the said dielectric; and

means for applying a third voltage to said source and a fourth voltage to said gate thereby to cause a current to be read indicating the presence or absence of a stored charge in said dielectric, the fourth voltage being between a fifth voltage sufficient to invert said channel with no charge in said charge trapping region and a sixth voltage sufficient to create a voltage beneath said third voltage at a point in said channel beneath an edge of said charge trapping region with charge stored therein.

36. The memory cell according to claim 35 wherein said dielectric further comprises,

a first layer of silicon dioxide formed on said substrate:

a layer of silicon nitride formed on said first layer of silicon dioxide, said layer of silicon nitride being capable of retaining charge in a selected portion thereof; and

a second layer of silicon dioxide formed on said silicon nitride, said second layer of silicon dioxide assisting said silicon nitride in retaining the charge trapped in the charge trapping region thereof despite the electric fields generated therein.

37. A programmable read only memory (PROM) cell, comprising:

a semiconductor substrate of a first conductivity type;

a source comprising a region of said semiconducting substrate doped to have a conductivity opposite that of said semiconducting substrate;

a drain spaced from said source, comprising a region of said semiconducting substrate doped to have a conductivity opposite that of said semiconducting substrate;

a channel formed in the space between said source and said drain within said semiconducting substrate;

a first insulating layer overlaying and covering said channel;

a non conducting charge trapping layer formed on and overlaying said first insulating layer;

a second insulating layer formed on and overlaying said non conducting charge trapping layer;

a gate comprising an electrically conductive material formed on and overlaying said second insulating layer; and

wherein said charge trapping layer is formed so as to receive and retain a first selected amount of charge in a region of said non-conducting, charge-trapping layer close to and above said drain, said charge-trapping layer comprising a layer of silicon nitride having a thickness selected to ensure that the lateral electric field associated with the trapped charge is below the lateral electric field which would cause significant lateral diffusion of the stored charge and said first selected amount of charge is sufficient to cause a desired increase in the threshold voltage required to invert said channel when said cell is read in the reverse direction but is not sufficient to cause the same desired increase in the threshold voltage required to invert the channel when the cell is read in the forward direction.

38. The memory cell according to claim 37, wherein the thickness of the silicon nitride is selected to reduce the lateral electric field within the charge storage region to beneath a selected value thereby to reduce the lateral diffusion of the stored charge in the silicon nitride and thereby to limit the reduction in the threshold voltage of the portion of the channel beneath said charge storage region due to this lateral diffusion to less than a selected amount.

39. The memory cell according to claim 38, wherein the reduction in the threshold voltage of the portion of the channel beneath said charge storage region due to lateral diffusion of the stored charge is less than ten percent of the threshold voltage of this portion of the channel before the lateral diffusion.

40. The memory cell according to claim 38, wherein the reduction in the threshold voltage of the portion of the channel beneath said charge storage region due to lateral diffusion of the stored charge is less than five percent of the threshold voltage of this portion of the channel before the lateral diffusion.