Compression and decompression scheme performed on shared workstation memory by media coprocessor

• US 5,768,445 A
• Filed: 09/13/1996
• Issued: 06/16/1998
• Est. Priority Date: 09/13/1996
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Silicon Graphics Incorporated (Graphics Properties Holdings, Inc.)
• Inventors: Troeller, Mark W., Fuccio, Michael L., Moreton, Henry P., Hagemark, Bent, Lau, Te-Li
• Primary Examiner(s): Boudreau, Leo H.
• Assistant Examiner(s): Tadayon, Bijan
• Application Number:
  US08/713,599
• Time in Patent Office: 641 Days
• Field of Search: 382/232, 382/233, 382/234, 382/235, 382/236, 382/238, 382/239, 382/290, 382/244, 382/245, 382/246, 382/248, 382/250, 382/251, 382/276, 382/302, 382/303, 382/304, 382/305, 382/306, 382/309, 382/166, 382/307, 382/311, 348/645, 348/180, 711/100, 711/111, 711/112, 711/113, 711/114, 711/117, 711/120, 711/121, 711/122, 711/127, 711/128, 711/129, 711/130, 711/147, 711/153, 711/157, 711/165, 711/167, 711/168, 711/169, 711/170, 711/173, 711/211
• US Class Current: 382/305
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/61 in combination with predictive coding

Abstract

This relates to a general purpose circuit that maximizes the computing power of a Unix workstation or other computer system for processing image or other data in accordance with a selected one or ones of several alternative compression and decompression algorithms. This dynamically allocates system memory for storage of both compressed and uncompressed data and ensures adequate compression and decompression rates.

Claims

1. In a computer system having system memory, a system controller for controlling access to system memory, and a central processor for manipulating data stored in said system memory, a compression and decompression engine for compressing and decompressing data stored in said system memory, said compression and decompression engine comprising:

a first processor for performing cosine transformation on a YCrCb value representing visible pixels into the frequency domain, said central processor adapted to configure said first processor to compress or decompress said data in accordance with a selected compression or decompression algorithm;

a second processor for entropy encoding or decoding a bit stream of frequency domain data, said central processor adapted to configure said second processor to compress or decompress said data in accordance with said selected compression or decompression algorithm;

memory, associated with said first and second processors, said memory divided into at least three independently addressable memory banks; and

a dynamic memory allocation (DMA) controller associated with said first and second processors, for transferring said data between system memory and said memory;

wherein said DMA controller is adapted to transfer a first portion of said data from said system memory to a first of said at least three independently addressable memory banks to initiate a compression or decompression of said data, said DMA controller further adapted to transfer data to a second of said at least three independently addressable memory banks while said first and second processors compress or decompress said data in said first of said at least three independently addressable memory banks, said DMA controller further adapted to transfer compressed or decompressed data in a third of said at least three independently addressable memory banks to said system memory.

2. The compression and decompression engine of claim 1 wherein said DMA controller further comprises:

means for acquiring mastership of a system bus and transferring a unit of granularity of data to one of said at least three independently addressable memory banks.

3. The compression and decompression engine of claim 1 further comprising:

arbiter means and bus means for ensuring said first processor has highest priority access to each of said at least three independently addressable memory banks.

4. The compression and decompression engine of claim 1 wherein said compressed or decompressed data provided by said first and second processors is stored in said third of said at least three independently addressable memory banks.

5. The compression and decompression engine of claim 1 wherein said data comprises uncompressed real-time video data stored to a page of system memory, said DMA controller further comprising means for locating said page of real-time video data and transferring said real-time video data to said independently addressable banks of memory for compression and for transferring compressed data from said independently addressable banks of memory to a second page of said system memory in real-time.

6. The compression and decompression engine of claim 5, wherein said central processor is adapted to point said compression/decompression engine to one of a plurality of system memory pages, each of said plurality of system memory pages comprising data for compression or decompression.

7. The compression and decompression engine of claim 5, wherein the rate of compression and decompression is sufficient for real-time compression and decompression of video data.

8. The compression and decompression engine of claim 6, wherein said compression and decompression of real-time video data in accordance with said selected compression or decompression algorithm further comprises means for converting said video data from the spatial domain to the frequency domain for compression and from the frequency domain to the spatial domain for decompression.

9. In a computer system having a central processor and a system memory for storing data, a compression and decompression coprocessor comprising:

a local data memory having sufficient storage space for storing only a portion of data in said system memory;

processor means, associated with said local data memory for processing the data resident in said local data memory in accordance with a compression or decompression algorithm;

means for transferring a portion of said data from said system memory to said local data memory at a rate sufficient to maintain operation of said processor means and for transferring processed data from said local data memory to said system memory; and

means associated with said data transferring means for identifying the location of said unprocessed data in said system memory and the location for storing processed data in said system memory.

10. The compression and decompression coprocessor of claim 9 wherein said system memory comprises storage for the equivalent of up to six frames of uncompressed video data captured in real-time.

11. The compression and decompression coprocessor of claim 10 wherein said system memory further comprises dynamically allocable storage for processed data.

12. The compression and decompression coprocessor of claim 10 wherein said central processor selectively operates on said uncompressed video data stored in said system memory prior to the transfer of data from said system memory to said local data memory.

13. In a computer system, a method for controlling data flow during the compression and decompression of image data with a compression engine, said method comprising the steps of:

a) collecting image data in a region of system memory associated with a computer system;

b) configuring a compression engine with a selected compression algorithm;

c) transferring a portion of said image data comprising at least one unit of granularity of data to a first local memory associated with said engine;

d) concurrently compressing the transferred portion of said image data and transferring an additional portion of said image data to a second local memory associated with said engine;

e) storing in a third local memory associated with said engine, the compressed portion of said image data transferred to said first local memory in step c);

f) transferring to said system memory the compressed portion of said image data stored in said third local memory in step e);

g) concurrently compressing the portion of said image data transferred to said second local memory in step f) and transferring an additional portion of said image data to said third local memory;

h) storing in said first local memory, the compressed portion of said image data stored in said second local memory in step f);

i) transferring the compressed portion of said image data stored in said first local memory in step h) to said system memory;

j) concurrently compressing the portion of said image data transferred to said third local memory in step g) and transferring an additional portion of said image data to said first local memory;

k) storing to said second local memory, the compressed portion of said image data stored in said third local memory in step i);

l) transferring the compressed portion of said image data stored in said second local memory in step k) to said system memory; and

m) repeating steps c) through l) so that said image data in said system memory is transferred from said system memory, compressed, and transferred back to said system memory.

14. In a computer system, a method for utilizing system memory during the collection of data from a data source for compression or decompression with a compression and decompression engine, said method comprising the steps of:

a) collecting data in a plurality of pages in system memory;

b) transferring a first portion of said data in one of said plurality of pages to a local memory associated with a compression and decompression engine;

c) concurrently transforming said data in accordance with a selected compression or decompression algorithm while transferring a second portion of said data to said local memory; and

d) transferring the data transformed in step c) from said local memory to one of a second plurality of pages in said system memory.

15. The method as recited in claim 14 wherein steps a-d) are performed such that said compression and decompression engine is time-shared by more than one data source.