System and method for synchronizing multiple processors during power-on self testing

• US 5,768,585 A
• Filed: 11/21/1995
• Issued: 06/16/1998
• Est. Priority Date: 11/21/1995
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Murthi, Raghu, Tetrick, R. Scott
• Primary Examiner(s): Kriess, Kevin A.
• Application Number:
  US08/561,627
• Time in Patent Office: 938 Days
• Field of Search: 395/651, 395/652, 395/653, 395/200.55, 395/200.5, 395/200.51, 395/200.52, 395/712
• US Class Current: 713/2
• CPC Class Codes: G06F 11/2284 by power-on test, e.g. power-on self test [POST]
• CPC Class Codes: G06F 15/177 Initialisation or configuration control processor initialisation G06F9/4405
• CPC Class Codes: G06F 9/4405 Initialisation of multiprocessor systems

Abstract

A method for synchronizing testing of shared memory contained in a multi-processor computer system after reset. The method involves the steps of performing a wake-up procedure by a bootstrap processor on the other processors. Thus, the other processors can assist in testing the shared memory. Next, respective portions of the shared memory are allocated to each of the processors. Finally, upon completion of testing of its respective portion of the shared memory, each processor sets its unique storage unit synchronizing the processors at completion.

Claims

1. In a computer system including a shared memory, a first plurality of processors adapted to access the shared memory and a first storage element, a method for synchronizing testing of the shared memory comprises the steps of:

selecting one of said first plurality of processors as a bootstrap processor;

performing a wake-up procedure by said bootstrap processor on a second plurality of processors to determine how many of the second plurality of processors are operational;

allocating a respective portion of the shared memory targeted for testing to each of the operational processors;

testing of the shared memory by the operational processors in parallel; and

setting a unique storage unit within the first storage element by each of the operational processors after completion of testing of its respective portion of the shared memory.

2. The method according to claim 1, wherein said second plurality of processors in combination with said bootstrap processor is equivalent to said first plurality of processors.

3. The method according to claim 1, wherein said wake-up procedure includes the steps of transmitting an inter-processor interrupt signal from said bootstrap processor to each of said second plurality of processors.

4. The method according to claim 1, wherein said wake-up procedure includes the steps of

activating a reset signal coupled to each of said second plurality of processors;

and

deactivating said reset signal thereby synchronizing power-on self testing performed by said second plurality of processors.

5. The method according to claim 1, wherein said allocating step includes the step of communicating from said bootstrap processor to each of said second plurality of processors a respective processor number, data representing a storage size of said shared memory and a number of said operational processors, so as to determine a respective starting address and ending address defining said respective portion of the shared memory.

6. The method according to claim 1, wherein said allocating step includes the step of utilizing said bootstrap processor to determine, for each of said operational processors, a starting address and an ending address defining each respective portion of the shared memory.

7. The method according to claim 1, wherein prior to said setting step, the method further comprises the step of supporting arbitration by said first plurality of processors to obtain test instructions from a second storage element in order to test the shared memory.

8. In a computer system including a shared memory, a plurality of processors adapted to access the shared memory and a first storage element, a method for synchronizing testing of the shared memory comprises the steps of:

performing a wake-up procedure on at least one of the plurality of processors;

determining how many of the plurality of processors are operational;

allocating a different portion of the shared memory to each of the plurality of processors that are operational;

testing the allocated portion of the shared memory in parallel by each of the plurality of processors that are operational; and

setting a unique storage unit of the first storage element by each of the plurality of processors that are operational upon completion of testing of its allocated portion of the shared memory.

9. The method according to claim 8, wherein prior to said allocating step, the method further includes the step of initializing one of said plurality of processors as a bootstrap processor.

10. The method according to claim 9, wherein said wake-up procedure includes the step of transmitting an inter-processor interrupt signal from said bootstrap processor to each of said at least one of the plurality of processors.

11. The method according to claim 9, wherein said wake-up procedure includes the steps of

activating a reset signal coupled to each of said at least one of the plurality of processors;

and

deactivating said reset signal thereby synchronizing the testing performed by said plurality of processors.

12. The method according to claim 8, wherein prior to said setting step, the method further comprises the step of supporting arbitration by said plurality of processors to obtain test instructions from a second storage element in order to test the shared memory.