Method and apparatus for sharing hardward resources in a computer system

• US 5,768,598 A
• Filed: 02/15/1996
• Issued: 06/16/1998
• Est. Priority Date: 09/13/1993
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ravichandran, Krishnan, Marisetty, Suresh K.
• Primary Examiner(s): Harvey, Jack B.
• Assistant Examiner(s): CHUNG TRANS, XUONG MY
• Application Number:
  US08/602,253
• Time in Patent Office: 852 Days
• Field of Search: 395/726, 395/500, 395/733, 395/734, 395/280, 395/306, 395/309, 395/284, 395/800.11, 395/800.15
• US Class Current: 710/260
• CPC Class Codes: G06F 13/26 with priority control

Abstract

A method and apparatus for sharing a logic block between multiple peripheral/input/output I/O devices. A method and apparatus for generating a first interrupt in response to a request from one of the devices. A second interrupt is also generated. The second interrupt is recognized before the first interrupt, such that the second interrupt is handled first and causes the logic block to be configured for the requested device. Then the first interrupt is then handled in which the request to the desired device is serviced using the reconfigured hardware.

Claims

1. A method for sharing hardware resources between a plurality of devices wherein the hardware resources includes a configurable logic block, said method comprising the steps of:

generating a first interrupt in response to a request for one of the plurality of devices;

generating a second interrupt, wherein the second interrupt is recognized before the first interrupt;

handling the second interrupt, including the step of dynamically reconfiguring hardware connections in the configurable logic block to provide a compatible interface to said one of the plurality of devices to enable access thereto; and

then

handling the first interrupt including the step of accessing said one of the plurality of devices such that a response to the request from said one of the plurality of devices is performed.

2. The method defined in claim 1 wherein the second interrupt is generated in response to the first interrupt.

3. The method defined in claim 1 wherein the first interrupt and the second interrupt are generated simultaneously.

4. The method defined in claim 3 wherein the second interrupt has a higher priority than the first interrupt, such that the second interrupt is recognized before the first interrupt.

5. The method defined in claim 3 wherein the first interrupt and second interrupt are sequenced, such that the second interrupt is recognized before the first interrupt.

6. The method defined in claim 1 wherein the hardware of the configurable logic block is configured transparently to the handling of the first interrupt.

7. A method for obtaining service for one of a plurality of devices coupled to a shared logic block in a computer system, wherein the shared logic block provides for communication between the computer system and the plurality of devices, wherein each of the plurality of devices has an interface protocol used when communicating in the computer system and wherein the plurality of devices are addressed using a single address, the method comprising the steps of:

generating a first interrupt in response to a service request from one of said plurality of devices;

generating a second interrupt in response to the first interrupt, wherein the second interrupt is recognized before the first interrupt;

invoking a first handler for handling the second interrupt, wherein the first handler dynamically reconfigures hardware connections in the shared logic block to create an interface for said one of the plurality of devices to allow access thereto; and

then

invoking a second handler for handling the first interrupt to service said one of the plurality of devices, wherein the first handler initializes the shared logic block transparently to the second handler, such that the shared logic block is configured to the interface protocol of said one of the plurality of devices transparently to an operating system to handle the service request.

8. The method defined in claim 7 wherein the first interrupt and second interrupt are generated simultaneously.

9. The method defined in claim 8 wherein the second interrupt has a higher priority than the first interrupt, such that the second interrupt is recognized before the first interrupt.

10. The method defined in claim 7 wherein the shared logic block is dynamically reconfigured transparently to the service request being completed.

11. A method for handling a request by one of a plurality of devices mapped to one location and using a shared logic block in a computer system, wherein the computer system is running an application program, and wherein each of the plurality of devices has an interface protocol required for use when communicating in the computer system, the method comprising the steps of:

identifying said one of the plurality of devices;

dynamically configuring hardware connections in the shared logic block, transparently to the application program, to create an external interface to support the interface protocol of said one of the plurality of devices; and

accessing said one of the plurality of devices using the shared logic block.

12. The method defined in claim 11 wherein the step of identifying includes identifying said one of the plurality of devices by examining the location of an instruction being used.

13. The method defined in claim 11 wherein the step of identifying includes the step of generating a first interrupt by said one of the plurality of devices.

14. The method defined in claim 13 wherein the step of generating the first interrupt includes the step of generating a second interrupt that is recognized before the first interrupt and wherein said second interrupt causes the hardware of the shared logic block to be dynamically reconfigured to create an external interface to support the interface protocol of said one of the plurality of devices.

15. The method defined in claim 14 wherein the first and second interrupts are generated simultaneously.

16. The method defined in claim 15 wherein the first interrupt and the second interrupt are sequenced, such that the second interrupt is recognized before the first interrupt.

17. The method defined in claim 15 wherein the second interrupt has a higher priority than the first interrupt, such that the second interrupt is recognized before the first interrupt.

18. A computer system comprising:

a bus for communicating information;

a processor coupled to the bus to execute a plurality of instructions;

a plurality of devices for communicating information with the processor, wherein each of the plurality of devices communicates with the processor according to an interface protocol; and

programmable logic coupled to the plurality of devices and the bus to provide a communication path between the plurality of devices and the bus, wherein the processor communicates with said plurality of devices through said programmable logic, wherein the programmable logic is programmed to dynamically reconfigure internal hardware connections therein, transparently to an application program and operating system running on the processor, to create an interface that conforms to the interface protocol of one of the plurality of devices when said one of the plurality of devices is to communicate with the processor.

19. The computer system defined in claim 18 wherein said one of the plurality of devices is to communicate with the processor in response to the execution of a instruction of the application program by said processor.

20. The computer system defined in claim 19 further comprising means coupled to the processor for generating an interrupt which is transparent to the operating system and the application program, and wherein the interrupt causes the processor to reprogram a shared logic block.

21. The computer system defined in claim 20 further comprising means coupled to said one of the plurality of devices for generating a first interrupt when said one of the plurality of devices is identified for communication with the processor, wherein said first interrupt causes generation of a second interrupt, wherein the second interrupt causes the processor to reprogram the shared logic block and the first interrupt causes communication to occur between said one of the plurality of devices and the processor after said shared logic block has been reconfigured.

22. The computer system defined in claim 21 wherein the first interrupt and the second interrupt are generated simultaneously and the second interrupt is recognized before the first interrupt.

23. The computer system defined in claim 22 wherein the second interrupt has a higher priority than the first interrupt.

24. The computer system defined in claim 21 wherein the first interrupt and the second interrupt are sequenced, such that the second interrupt is generated after and recognized before the first interrupt.

25. A computer system comprising:

a bus for communicating information;

a processor coupled to the bus to execute a plurality of instructions in support of an applications program;

a plurality of devices that operate with the processor, wherein each one of the plurality of devices communicates according to an interface protocol;

a programmable logic coupled to the plurality of devices and the bus as a pathway for communication between the processor and the plurality of devices, wherein the programmable logic is shared by the plurality of devices; and

an interrupt controller coupled to receive a first signal from the programmable logic and to provide the processor with a first interrupt and a second interrupt, wherein the interrupt controller generates the first interrupt and the second interrupt in response to the first signal and wherein the second interrupt causes the processing means to dynamically reconfigure hardware connections in the programmable logic to create an interface for said one of the plurality of devices that conforms to the interface protocol of the said one of the plurality of devices and the first interrupt causes said one of the plurality of devices to be accessed, such that the programmable logic is reconfigured before said one of the plurality of devices is accessed.

26. The computer system defined in claim 25 wherein said one of the plurality of devices communicates with the processor in response to the execution of an instruction of the application program by said processor, and wherein the programmable logic is programmed transparently to the application program and operating system.

27. The computer system defined in claim 25 wherein the second interrupt is transparent to the operating system and the application program, and wherein the second interrupt causes the processor to reprogram a shared logic block.

28. The computer system defined in claim 25 wherein said first interrupt causes communication to occur between said one of the plurality of devices and the processor.

29. The computer system defined in claim 25 wherein the first interrupt and the second interrupt are generated simultaneously and the second interrupt is reconfigured before the first interrupt.

30. The computer system defined in claim 25 wherein the second interrupt has a higher priority than the first interrupt.

31. The computer system defined in claim 25 wherein the first interrupt is generated before the second interrupt, and wherein the first interrupt and the second interrupt are sequenced, such that the second interrupt is recognized before the first interrupt.