Reduced area of crossbar and method of operation

• US 5,768,609 A
• Filed: 06/07/1995
• Issued: 06/16/1998
• Est. Priority Date: 11/17/1989
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Balmer, Keith, Gove, Robert J., Guttag, Karl Marion, Ing-Simmons, Nicholas Kerin
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): MOHAMED, AYNI Y
• Application Number:
  US08/483,657
• Time in Patent Office: 1,105 Days
• Field of Search: 395/325, 395/375, 395/800, 395/400
• US Class Current: 712/11
• CPC Class Codes: G06F 15/17375 One dimensional, e.g. linear array, ring

Abstract

There is disclosed a multi-processor system and method arranged, in one embodiment, as an image and graphics processor. The image processor is structured with several individual processors all having communication links to several memories. A crossbar switch serves to establish the processor memory links. The entire image processor, including the individual processors, the crossbar switch and the memories, is contained on a single silicon chip.

Claims

1. A multi-processing system comprising:

a plurality of n processors, each of said processors operable from an instruction stream provided from a memory source for controlling a process, said process relying on the movement of data to and from one or more addressable memories, each processor having a data port and a separate instruction port;

a plurality of m memory sources, each memory source having a unique addressable space;

switch matrix having first links connected to said memories, second links connected to said data ports of said processors and a selectively splittable third link having n splittable sections, each splittable section connected to said instruction port of a corresponding one of said processors, said switch matrix selectively connecting said first and second links whereby said data port of each of said processors may access any of said m memory sources, said switch matrix selectively connecting said first links and said third link when said third link is split for supplying said instruction stream for each of said processors from a corresponding memory source and said switch matrix selectively connecting said first links and said third link when said third link is not split for supplying said instruction stream for each of said processors from a predetermined common memory source.

2. The multi-processing system set forth in claim 1 where m is greater than n.

3. The multi-processing system set forth in claim 1 wherein said switch matrix contains a plurality of crosspoints disposed at intersections between said first links and second and third links operable on a cycle by cycle basis to effect said interconnecting of processors and memory sources.

4. The multi-processing system set forth in claim 3 wherein said switch matrix further includes circuitry for responding to provided addresses for controlling said crosspoints.

5. The multi-processing system set forth in claim 3 wherein each said crosspoint includes prioritization control circuitry to sequence simultaneous processor access attempts to the same memory source.

6. The multi-processing system set forth in claim 5 wherein said prioritization control circuitry includes sequential token passing circuitry.

7. The multi-processing system set forth in claim 6 wherein said sequential token passing circuitry includes circuitry for insuring lowest priority memory access to the one of said processors which last successfully assessed said memory source corresponding to said crosspoint.

8. The multi-processing system set forth in claim 1 wherein said switch matrix includes crosspoints for interconnecting said first, second and third links and wherein said n processors, said m memory sources and said switch matrix, including said first, second and third links and said crosspoints, are all constructed on a single integrated circuit, and wherein said first, second and third links and said crosspoints of said switch matrix are distributed across said single integrated circuit in spacial relationship with said n processors and said m memory sources.

9. The multi-processing system set forth in claim 7, further comprising:

a separate processor having a data port connected to a separate processor second link of said switch matrix; and

wherein said prioritization control circuitry of each crosspoint of said switch matrix connected to said separate processor second link allows said separate processor access to any of said n memory sources.

10. The multi-processing system set forth in claim 7, further comprising:

a separate processor having a data port connected to a separate processor second link of said switch matrix; and

wherein said prioritization control circuitry of each crosspoint of said switch matrix connected to said separate processor second link allows said separate processor access to any of said n memory sources, said prioritization control circuitry giving the lowest priority for access to any memory source to said separate processor.

11. The multi-processing system set forth in claim 1 wherein:

said number of memory sources m is an integral multiple k of the number of processors n;

said switch matrix includes crosspoints for interconnecting said first, second and third links;

said n processors are disposed linearly;

said m memory sources are disposed linearly opposite said n processors, a corresponding k of said memory sources disposed opposite each of said processors; and

said switch matrix is disposed between said n processors and said m memory sources, said crosspoints connected to said second and third links of each of said n processors further connected to said first links of said corresponding k of said memory sources and disposed between said one of said n processors and said corresponding k of said memory sources.

12. The multi-processor system set forth in claim 1 further comprising

an external memory not directly connected to said switch matrix;

a transfer processor connected to said switch matrix for access to said plurality of memory sources and to said external memory, said transfer processor controlling data transfer from a selected one of said m memory sources via said switch matrix to said external memory and data transfer form said external memory to a selected one of said m memory sources via said switch matrix.

13. The multi-processor system claimed in claim 1, further comprising:

an external memory for storing instructions for each of said n processors not directly connected to said switch matrix;

said plurality of memory sources includes an instruction memory corresponding to each of said n processors, each instruction memory stores only a portion of the instructions for said corresponding processor; and

wherein each of said n processors includes;

a program counter having stored therein an address of a next instruction,

an instruction fetch circuit for supplying to said instruction port said address stored in said program counter for fetching an instruction stored at said address,

a cache logic circuit connected to said program counter for determining if the instruction corresponding to the address stored in said program counter is stored in said corresponding instruction memory; and

said multi-processor system further comprising a transfer processor connected to said cache logic circuit of each of said processors, said switch matrix and said external memory, said transfer processor transferring an instruction corresponding to the address stored in said program counter of one of said n processors from said external memory to said corresponding instruction memory via said switch matrix if said corresponding cache logic circuit indicates the instruction is not stored in said corresponding instruction memory.

14. The method of operating a multi-processing system having a plurality of n processors, each processor operable from an instruction stream provided from a memory source for controlling a process relying upon movement of data to and from one or more addressable memory spaces, each processor having at least one data port and a separate instruction port, a plurality of m memory sources, each memory source having a unique addressable memory space and a switch matrix connected to the data port and the instruction port of the n processors and to the m memory sources, said switch matrix containing a plurality of crosspoints, said method comprising the steps of:

selectively connecting via the switch matrix the data port of each of said n processors to any of said m memory sources;

selectively connecting via the switch matrix the instruction port of each of said n processors to only a predetermined corresponding subset of said m memory sources; and

operating said crosspoints on a cycle by cycle basis to effect said interconnecting of processors and memories.

15. The method set forth in claim 14 further including the step of:

responding to an address provided by said data port of one of said n processors for controlling said switch matrix to connect said data port of said one of said n processors to a one of said m memory sources whose unique addressable memory space includes said address.

16. The method set forth in claim 14, wherein said crosspoint includes a prioritization control system and wherein said method further includes the step of:

sequencing simultaneous processor access attempts to the same memory.

17. The method set forth in claim 16 wherein said prioritization system includes the step of sequential token passing.

18. The method set forth in claim 17 wherein said token passing step includes the step of:

insuring lowest priority memory access to the processor which last successfully accessed the memory associated with said crosspoint.

19. The method set forth in claim 18 further comprising the step of:

allowing separate processors to have access to any of said instruction or data memories over said switch matrix links, and wherein said prioritization system further includes the step of giving lowest priority to said separate processor for each said memory.

20. The method set forth in claim 14, wherein:

said step of selectively connecting via the switch matrix the instruction port of each of said n processors to only a predetermined corresponding subset of said m memory sources includes connecting via the said switch matrix the instruction port of each processor to a corresponding memory source.

21. The method set forth in claim 14, wherein:

said step of selectively connecting via the switch matrix the instruction port of each of said n processors to only a predetermined corresponding subset of said m memory sources includes connecting via the said switch matrix the instruction port of all of the processors to a predetermined common memory source.

22. The method set forth in claim 14, wherein:

said step of selectively connecting via the switch matrix the instruction port of each of said n processors to only a predetermined corresponding subset of said m memory sources includes selectively connecting via the said switch matrix the instruction port of each processors to either a selected one of a corresponding memory source or to a predetermined common memory source.

23. The method forth in claim 14, said multi-processing system further having an external memory not directly connected to said switch matrix, and a transfer processor connected to said switch matrix and said external memory, said method further comprising the steps of:

transferring data from a selected one of said m memory sources via said switch matrix and said transfer processor to said external memory; and

transferring data form said external memory to a selected one of said m memory sources via said switch matrix and said transfer processor.

24. The method set forth in claim 14, said multi-processor system further having an external memory for storing instructions for each of said n processors not directly connected to said switch matrix and a transfer processor connected to said switch matrix and said external memory, said plurality of memory sources including n instruction memory sources, one corresponding to each of said n processors, each instruction memory storing only a portion of the instructions for said corresponding processor, said method further comprising the steps of:

determining at each processor if a next instruction is stored in said corresponding instruction memory;

if said next instruction is stored in said corresponding instruction memory, fetching said next instruction from said corresponding instruction memory via said instruction port and said switch matrix; and

if said next instruction is not stored in said corresponding instruction memory, transferring said next instruction from said external memory to said corresponding instruction memory via said switch matrix and said transfer processor and thereafter fetching said next instruction from said corresponding instruction memory via said instruction port and said switch matrix.

25. An image processing system comprising:

a master processor for controlling said image processing system, said master processor having a data port;

a plurality of n processors, each of said processors operable from an instruction stream provided from a memory source for controlling a process, said process relying on the movement of data to and from one or more addressable memories, each processor having a data port and an instruction port;

a plurality of m memory sources, each memory source having a unique addressable space;

a switch matrix having first links each connected to a corresponding one of said m memories sources, second links each connected to a corresponding one of said data port of said master processor and said data ports of said n processors and a selectively splittable third link having n splittable sections, each splittable section connected to a corresponding one of said instruction ports of said n processors, said switch matrix

selectively connecting said first and second links whereby said data port of said master processor may access any of said m memory sources,

selectively connecting said first and second links whereby said data port of each of said processors may access any of said m memory sources,

selectively connecting said first links and said third link when said third link is not split for connecting said instruction port of each of said processors to a predetermined common memory source, and

selectively connecting said first links and said third link when said third link is split for connecting said instruction port of each of said processors to a corresponding one of said m memory sources.

26. The image processing system set forth in claim 25, further comprising:

an external memory; and

a transfer processor connected to said switch matrix and said external memory for transferring data between said external memory and said m memory sources via said switch matrix.