Vehicle based LAN a communication buffer memory having at least one more number of storage areas for receive status and source address than the number of areas for receive data

• US 5,768,625 A
• Filed: 06/27/1995
• Issued: 06/16/1998
• Est. Priority Date: 03/29/1991
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Nita, Takeshi, Matsumoto, Norio, Yamaguchi, Yuichiro, Suda, Shinji, Satou, Yoshikazu, Yokoyama, Etsuya, Muramatsu, Kikuo, Okamoto, Yasushi, Arimoto, Akiya
• Primary Examiner(s): DINH, DUNG C
• Application Number:
  US08/495,335
• Time in Patent Office: 1,085 Days
• Field of Search: 395/250, 395/872-876, 395/200.6, 395/200.62, 395/200.64, 395/200.8
• US Class Current: 710/56
• CPC Class Codes: H04L 12/40 Bus networks
• CPC Class Codes: H04L 12/40013 Details regarding a bus controller
• CPC Class Codes: H04L 12/40032 Details regarding a bus interface enhancer
• CPC Class Codes: H04L 12/4015 by scheduling the transmission of messages at the communication node
• CPC Class Codes: H04L 12/40163 by assigning priority to messages according to a message field
• CPC Class Codes: H04L 12/413 with random access, e.g. carrier-sense multiple-access with collision detection [CSMA-CD]
• CPC Class Codes: H04L 2012/40273 the transportation system being a vehicle
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9021 Plurality of buffers per packet
• CPC Class Codes: H04L 49/9026 Single buffer per packet
• CPC Class Codes: H04L 49/9031 Wraparound memory, e.g. overrun or underrun detection
• CPC Class Codes: H04L 49/9047 including multiple buffers, e.g. buffer pools
• CPC Class Codes: H04L 49/9057 Arrangements for supporting packet reassembly or resequencing

Abstract

A primary object is to provide a communication apparatus, in particular, its buffer memory which conforms mainly to specifications of SAE-J1850 or ISO-9141. In the buffer memory, there are provided: at least, one more status registers storing information associated with the state of respective information to be transmitted and received, than the number of buffers storing information to be transmitted and received; at least, the same number of transmission error registers storing information associated with the transmitting state of information to be transmitted, as the buffers storing information to be transmitted; at least, one more receiving error registers storing information associated with the receiving state of information to be received, than the buffers storing information to be received; at least, one more source address registers storing information associated with the other communication apparatus which has transmitted respective information to be received, than the buffers storing information to be received; and at least, the same number of response information registers storing information responded from the communication apparatus which is to receive information when the information to be transmitted is transmitted, as the buffers storing information to be transmitted.

Claims

1. A communication apparatus which comprises a buffer memory having n number of transmitting buffers each storing one unit of information to be transmitted to other communication apparatus respectively and m number of receiving buffers each storing one unit of information to be received from other communication apparatus respectively, and which temporarily stores information to be transmitted to other communication apparatus in said transmitting buffer and thereafter transmits it, and temporarily stores information to be received from the other communication apparatus in said receiving buffer and thereafter receives it,

wherein said buffer memory is provided with:

at least n+m+1 number of status registers each for storing information relating to status of said information in said buffers to be transmitted and received;

at least n number of transmitting error registers each for storing information relating to status of one unit of information in said buffers to be transmitted; and

at least m+1 number of receiving error registers each for storing information relating to status of said information in said buffers to be received.

2. A communication apparatus which comprises a buffer memory having n number of transmitting buffers each storing one unit of information to be transmitted to other communication apparatus respectively and m number of receiving buffers each storing one unit of information to be received from other communication apparatus respectively, and which temporarily stores information to be transmitted to the other communication apparatus in said transmitting buffer and thereafter transmits it, and temporarily stores information to be received from other communication apparatus in said receiving buffer and thereafter receives it, respectively,

wherein said buffer memory is provided with at least m+1 number of storage areas, each for storing source address information relating to remote communication apparatus from which said information is transmitted to facilitate retransmission of data which could not be accommodated by said receiving buffers.

3. A communication apparatus which comprises a buffer memory having n number of transmitting buffers each storing one unit of information to be transmitted to other communication apparatus respectively and m number of receiving buffers each storing one unit of information to be received from other communication apparatus respectively, and which temporarily stores information to be transmitted to other communication apparatus in said transmitting buffer and thereafter transmits it, and temporarily stores information to be received from the other communication apparatus in said receiving buffer and thereafter receives it,

wherein said buffer memory is provided with:

at least n+m+1 number of status registers each for storing information relating to status of said information in said buffers to be transmitted and received;

at least n number of transmitting error registers each for storing information relating to status of said information in said buffers to be transmitted;

at least m+1 number of receiving error registers each for storing information relating to status of said information in said buffers to be received;

at least m+1 number of source address registers each for storing information relating to another communication apparatus from which information to be received is transmitted; and

at least n number of returning information registers each for, when information to be transmitted is transmitted, storing information being returned from another communication apparatus by which additional information to be transmitted may be retrieved.

4. A communication apparatus as set forth in claim 3, wherein each of said n number of transmitting buffers corresponds to one of said at least n+m+1 number of status registers, one of said at least n number of transmitting error registers, and one of said at least n number of returning information registers respectively.

5. A communication apparatus as set forth in claim 3, wherein each of said m number of receiving buffers corresponds to one of said at least n+m+1 number of status registers, one of said at least m+1 number of receiving error registers, and one of said at least m+1 number of source address registers respectively.

6. A communication apparatus as set forth in claim 3, wherein each of said n number of transmitting buffers corresponds to one of said at least n+m+1 number of status registers, one of said at least n number of transmitting error registers, and one of said at least n number of returning information registers respectively, and

each of said m number of receiving buffers corresponds to one of said at least n+m+1 number of status registers, one of said at least m+1 number of receiving error registers, and one of said at least m+1 number of source address registers respectively.

7. A communication apparatus which comprises:

a transmitting buffer group consisting of n number of transmitting buffers each of which store one unit of information in order to temporarily store information to be transmitted to other communication apparatus and thereafter output it;

a receiving buffer group consisting of m number of receiving buffers each of which stores one unit of information in order to temporarily store information to be received from other communication apparatus and thereafter receive it;

at least n+m+1 number of status registers, each of which stores information relating to status of said information in said buffers to be transmitted and received;

at least n number of transmitting error registers each of which stores information relating to transmitting status of said information in said buffers to be transmitted;

at least m+1 number of receiving error registers each of which stores information relating to receiving status of said information in said buffers to be received;

at least m+1 number of source address registers each of which stores information relating to other communication apparatus having transmitted information to be received; and

at least n number of returning information registers each of which, when information to be transmitted is transmitted, stores information being returned from another communication apparatus to permit additional information to be transmitted;

further comprising;

transmitting buffer designating means for designating usable ones of said transmitting buffers in the case where the information to be transmitted to another communication apparatus is stored in one of transmitting buffers of said transmitting buffer group;

receiving buffer designating means for designating usable ones of said receiving buffers in the case where the information to be received from another communication apparatus is stored in one of receiving buffers to said receiving buffer group;

status register designating means for designating ones of said at least n+m+1 number of status registers corresponding to said designated transmitting buffers or receiving buffers in the case where any transmitting buffer or any receiving buffer is designated by said transmitting buffer designating means or receiving buffer designating means;

transmitting error register designating means for designating one of said at least n number of transmitting error registers corresponding to said designated transmitting buffer in the case where any transmitting buffer is designated by said transmitting buffer designating means;

returning information register designating means for designating one of said at least n number of returning information registers corresponding to said designated transmitting buffer in the case where any transmitting buffer is designated by said transmitting buffer designating means;

receiving error register designating means for designating one of said at least m+1 number of receiving error registers corresponding to said designated receiving buffer in the case where any receiving buffer is designated by said receiving buffer designating means; and

source address register designating means for designating one of said at least m+1 number of source address registers corresponding to said designated receiving buffer in the case where any receiving buffer is designated by aid receiving buffer designating means.

8. A communication apparatus as set forth in claim 7, wherein said buffer memory further comprises:

a transmitting information counter for counting the number of buffers being used in said transmitting buffer group;

a receiving information counter for counting the number of buffers being used in said receiving buffer group;

means for detecting disagreement between said transmitting buffer designating means corresponding to the value of said transmitting information counter and designating value of said transmitting buffer designating means; and

means for detecting disagreement between said receiving buffer designating means corresponding to the value of said receiving information counter and designating value of said receiving buffer designating means.

9. A communication apparatus as set forth in claim 7, wherein said buffer memory further comprising:

a status number counter for counting the number of registers being used among said at least n+m+1 number of status registers; and

means for detecting disagreement between of said status register designating means corresponding to the counting value of said status number counter and designating value of said status register designating means.

10. A communication apparatus as set forth in claim 7, wherein said buffer memory further comprises:

transmitting information writing completion register to which addresses not allocated to each of said transmitting buffers may be allocated;

whereby, upon writing information to be transmitted in said buffer memory, each address allocated to said transmitting buffer is given to said buffer memory and predetermined information is outputted following the information to be transmitted, so that said predetermined information is stored in said transmitting information writing completion register.

11. A communication apparatus as set forth in claim 7, wherein said buffer memory further comprising:

receiving information reading completion register to which addresses not allocated to each said receiving buffer may be allocated;

whereby, upon reading information to be received in said buffer memory, each address allocated to said receiving buffer is given to said buffer memory and predetermined information is outputted, so that said predetermined information is stored in said receiving information reading completion register.