High conversion gain CMOS mixer
First Claim
1. A mixer comprising:
- a multiplier circuit comprising a plurality of transistors configured to receive a differential radio frequency (RF) signal and a differential local oscillator (LO) signal and to generate a differential intermediate frequency (IF) signal in accordance with mixing said RF signal and said LO signal;
an output stage circuit coupled to receive a differential current of said differential IF signal, said output stage comprising a low input impedance and a high output impedance for generating an output stage differential current approximately equal to said differential current from said IF differential signal; and
a gain stage coupled to said output stage for controlling conversion gain of said differential IF signal.
12 Assignments
0 Petitions
Accused Products
Abstract
A mixer contains a multiplier circuit that includes MOS transistors configured as a Gilbert multiplier cell without gain resistors such that a first and a second node are directly coupled to a folded cascode output stage. The mixer receives a differential radio frequency (RF) signal and a differential local oscillator (LO) signal, and it generates, at the first and second nodes, a differential intermediate frequency (IF) signal. The mixer further includes output and gain/filter stages coupled to the multiplier circuit. The output stage exhibits a low input impedance and a high output impedance, and it generates an output stage differential current approximately equal to the differential current of the IF differential signal. The gain/filter stage both controls conversion gain of the mixer, and it filters the high frequency components generated by said multiplier circuit. A capacitor, implemented as the gain/filter stage, and a folded-cascode circuit for the output stage are disclosed.
-
Citations
19 Claims
-
1. A mixer comprising:
-
a multiplier circuit comprising a plurality of transistors configured to receive a differential radio frequency (RF) signal and a differential local oscillator (LO) signal and to generate a differential intermediate frequency (IF) signal in accordance with mixing said RF signal and said LO signal; an output stage circuit coupled to receive a differential current of said differential IF signal, said output stage comprising a low input impedance and a high output impedance for generating an output stage differential current approximately equal to said differential current from said IF differential signal; and a gain stage coupled to said output stage for controlling conversion gain of said differential IF signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
-
-
9. A mixer comprising:
-
a multiplier circuit comprising; a first set of metal oxide semiconductor (MOS) transistors coupled to receive, at their gates, a radio frequency (RF) differential voltage signal and coupled, at their drains, to a first and second node; a second set of (MOS) transistors coupled to said first set of transistors and coupled to receive a local oscillator (LO) differential voltage, and to generate a differential intermediate frequency (IF) signal, including a differential current, in accordance with mixing said RF signal and said LO signal; a constant current source coupled to said second set of transistors and ground; an output folded-cascode stage coupled directly to said first and second nodes to receive said differential IF signal, said output stage comprising a low input impedance and a high output impedance, and said output stage for generating an output stage differential current approximately equal to said differential current from said IF differential signal; and a gain stage coupled to said output stage for controlling conversion gain of said output stage differential current. - View Dependent Claims (10, 11, 12, 13, 14, 15)
-
-
16. A downconverter mixer comprising:
-
a multiplier circuit comprising a plurality of transistors configured to receive a differential radio frequency (RF) signal and a differential local oscillator (LO) signal and to generate, at a first and second node, a differential intermediate frequency (IF) signal in accordance with mixing said RF signal and said LO signal, said transistors comprising; a first transistor and a second transistor coupled, at each drain, to said first node and said second node, respectively, and said first and said second transistors receive, at each gate, a positive leg of said radio frequency (RF) differential signal; a third transistor and a fourth transistor coupled, at each drain, to said second node and said first node, respectively, and said third and said fourth transistors receive, at each gate, a negative leg of said RF differential signal, said first and third transistors being coupled at the sources, and said second and fourth transistors being coupled at each source; a fifth transistor and sixth transistor, a drain of said fifth transistor being coupled to said sources of said first and third transistors and a drain of said sixth transistor being coupled to said sources of said second and fourth transistors, said fifth transistor receiving, at its gate, a positive leg of said LO differential signal, and said sixth transistor receiving, at its gate, a negative leg of said LO differential signal, and said fifth and sixth transistors being coupled at each source; a current source coupled at said sources of said fifth and sixth transistors and coupled to ground; a folded-cascode output stage coupled to said first and second nodes to receive said differential IF signal, said output stage comprising a low input impedance and a high output impedance, and said output stage generating an output stage differential current approximately equal to said differential current from said IF differential signal; and a capacitor coupled across said output stage for controlling conversion gain of said differential IF signal and for filtering high frequency components generated by said multiplier circuit. - View Dependent Claims (17, 18, 19)
-
Specification